BSV-RVFI-DII Library Wiki

BSV-RVFI-DII Library

CodeArtifact WIKI v1 · 5/30/2026

BSV-RVFI-DII is the cited RVFI-DII library/repository associated with TestRIG’s Direct Instruction Injection support. The TestRIG paper describes RVFI-DII as pairing DII instruction input with RVFI trace output for interactive verification, and says the RVFI-DII libraries provide reusable data structures, TCP-port connection support, and a mature DII unit for synchronizing injected instruction sequences with RVFI traces.

Overview

The BSV-RVFI-DII Library is the RVFI-DII library/repository cited by the TestRIG paper, which gives the repository URL as https://github.com/CTSRD-CHERI/BSV-RVFI-DII. In the paper’s terminology, RVFI-DII combines Direct Instruction Injection (DII) for instruction input with RVFI for trace output, enabling full interactive verification.

Role in RVFI-DII

The TestRIG paper states that its authors distribute data structures and libraries in several languages to make RVFI-DII connections over TCP ports easier to develop. It also describes a more capable DII unit as being available in the RVFI-DII libraries.

RVFI-DII is designed around a one-to-one relationship between injected DII instructions and RVFI trace entries. This matters for pipelined implementations because canceled or redirected instructions can otherwise desynchronize the input instruction stream from the output trace. The mature strategy described in the paper attaches a sequence ID to each RVFI instruction and carries it through the pipeline; instruction fetch requests each instruction ID from the DII sequence, allowing redirects to work naturally.

Bluespec interface context

The paper includes a Bluespec implementation sketch of the DII interface. In that sketch, a DII interface receives a reset command followed by a sequence of instructions, represented with fields such as whether the command is an instruction or reset, the time to inject the instruction, and the instruction word. For emulators, the paper describes this as replacing each fetched instruction with an encoding from the DII queue; for RTL designs, it notes that DII support is more complex.

Use in TestRIG-style verification

In the TestRIG workflow, instruction sequences can be sent over DII sockets and RVFI traces collected back for comparison. The paper’s QCVEngine uses QuickCheck to generate, compare, and shrink instruction sequences because DII decouples the instruction stream from control flow and does not associate injected instructions with memory addresses.

LINKED ENTITIES

3 links

RVFI-DII IMPLEMENTS

Bluespec USES

Randomized Testing of RISC-V CPUs using Direct Instruction Injection INTRODUCES

CITATIONS

6 sources

6 citations

[1] The TestRIG paper cites the BSV-RVFI-DII repository at https://github.com/CTSRD-CHERI/BSV-RVFI-DII. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[2] RVFI-DII uses DII for instruction input and RVFI for trace output, supporting full interactive verification. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[3] The authors distribute data structures and libraries in several languages to facilitate RVFI-DII connections over TCP ports. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[4] A more capable DII unit is available in the RVFI-DII libraries and uses sequence IDs to keep injected instructions synchronized with RVFI trace entries through pipeline redirects. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[5] The paper shows a Bluespec implementation of a DII interface that receives a reset command followed by a sequence of instructions. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[6] DII directly specifies the expected instruction sequence in the output trace and does not associate instructions with memory addresses, simplifying sequence generation and shrinking. Randomized Testing of RISC-V CPUs using Direct Instruction Injection