RVBS

CodeArtifact

RVBS is identified in TestRIG documentation as a reference RISC-V implementation and is listed among implementations used in the TestRIG verification ecosystem. The cited source associates RVBS with the RVFI-DII-based interface requirements used by TestRIG participants.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

RVBS is a code artifact referenced as a reference implementation in the TestRIG paper, alongside other RISC-V implementations such as Ibex, Piccolo, Flute, and Toooba. The paper lists the RVBS repository as https://github.com/CTSRD-CHERI/RVBS.

Role in the TestRIG ecosystem

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NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

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RELATIONSHIPS

4 connections

TestRIG ← evaluates 90% 4e

TestRIG has been used to test RVBS, a reference RISC-V implementation.

RISC-V implements → 100% 3e

RVBS is a reference RISC-V implementation.

RVFI-DII uses → 90% 3e

RVBS is instrumented with RVFI-DII to participate in the TestRIG ecosystem.

RVFI-DII implements → 90% 2e

RVBS is a RISC-V reference implementation instrumented with RVFI-DII.

LINKED ENTITIES

3 links

TestRIG EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

RVFI-DII USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] RVBS is identified as a reference implementation and is listed with other implementations including Ibex, Piccolo, Flute, and Toooba. Randomized Testing of RISC-V CPUs using Direct

[2] The source lists the RVBS repository as https://github.com/CTSRD-CHERI/RVBS. Randomized Testing of RISC-V CPUs using Direct

[3] TestRIG participants require an RVFI-DII interface, 8 MiB of memory at address 0x80000000, access faults for other addresses, and reset support to a known state. Randomized Testing of RISC-V CPUs using Direct

[4] Implementations participating in the TestRIG verification ecosystem must be extended with RVFI-DII instrumentation, and libraries/data structures are distributed to support RVFI-DII connections over TCP ports. Randomized Testing of RISC-V CPUs using Direct

[5] The source groups RVBS with implementations written in either SystemVerilog or Bluespec. Randomized Testing of RISC-V CPUs using Direct