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RVBS

CodeArtifact WIKI v1 · 5/27/2026

RVBS is identified in TestRIG documentation as a reference RISC-V implementation and is listed among implementations used in the TestRIG verification ecosystem. The cited source associates RVBS with the RVFI-DII-based interface requirements used by TestRIG participants.

Overview

RVBS is a code artifact referenced as a reference implementation in the TestRIG paper, alongside other RISC-V implementations such as Ibex, Piccolo, Flute, and Toooba. The paper lists the RVBS repository as https://github.com/CTSRD-CHERI/RVBS.

Role in the TestRIG ecosystem

The TestRIG paper describes a verification ecosystem in which implementations, models, and verification engines can be made interchangeable through a standardized communication interface. In the same context, RVBS is named as one of the implementations considered by the ecosystem.

TestRIG participants are expected to be architecturally identical in visible behavior. The paper states that participants require an RVFI-DII interface, 8 MiB of memory accessible at address 0x80000000, access faults for other addresses, and reset support to a known state with zeroed registers and zeroed 8 MiB of memory after a reset DII packet.

Interface expectations

The paper states that implementations participating in the TestRIG verification ecosystem must be extended with RVFI-DII instrumentation. It also notes that supporting data structures and libraries are distributed in several languages to facilitate RVFI-DII connections over TCP ports.

Implementation context

The source groups RVBS with implementations written in either SystemVerilog or Bluespec. The same passage characterizes RVBS specifically as a reference implementation, while describing other implementations in the group separately, such as Ibex and Piccolo as simple 32-bit implementations, Flute as a 5-stage in-order RV64 processor, and Toooba as a 64-bit superscalar out-of-order RISC-V processor.

LINKED ENTITIES

3 links
TestRIG EVALUATES
RISC-V IMPLEMENTS
RVFI-DII USES

CITATIONS

5 sources
5 citations
[1] RVBS is identified as a reference implementation and is listed with other implementations including Ibex, Piccolo, Flute, and Toooba. Randomized Testing of RISC-V CPUs using Direct
[2] The source lists the RVBS repository as https://github.com/CTSRD-CHERI/RVBS. Randomized Testing of RISC-V CPUs using Direct
[3] TestRIG participants require an RVFI-DII interface, 8 MiB of memory at address 0x80000000, access faults for other addresses, and reset support to a known state. Randomized Testing of RISC-V CPUs using Direct
[4] Implementations participating in the TestRIG verification ecosystem must be extended with RVFI-DII instrumentation, and libraries/data structures are distributed to support RVFI-DII connections over TCP ports. Randomized Testing of RISC-V CPUs using Direct
[5] The source groups RVBS with implementations written in either SystemVerilog or Bluespec. Randomized Testing of RISC-V CPUs using Direct