Flute

CodeArtifact

Flute is a RISC-V processor implementation described as a 5-stage in-order pipeline processor implementing RV64. In the TestRIG/RVFI-DII context, its simple single-issue design allowed instruction-cache replacement with a Direct Instruction Injection queue, and RVFI-DII work on Flute led to a sequence-ID synchronization design later available in RVFI-DII libraries and backported to Flute.

First seen 5/27/2026

Last seen 6/8/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Flute is a code artifact for a RISC-V processor implementation. The TestRIG paper identifies Flute as "a 5-stage in-order pipeline processor implementing RV64" and provides its repository as https://github.com/CTSRD-CHERI/Flute.^[1]

Role in TestRIG and RVFI-DII

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

TestRIG ← evaluates 95% 8e

TestRIG has been used to test the Flute RISC-V processor.

RISC-V implements → 100% 5e

Flute is a 5-stage in-order pipeline processor implementing RV64.

RVFI-DII implements → 90% 4e

Flute is instrumented with RVFI-DII for use in TestRIG.

RVFI-DII uses → 100% 3e

Flute is instrumented with RVFI-DII using a DII queue replacing the instruction cache.

LINKED ENTITIES

3 links

TestRIG EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

RVFI-DII USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Flute is a 5-stage in-order pipeline processor implementing RV64, and the paper provides its repository URL. Randomized Testing of RISC-V CPUs using Direct

[2] TestRIG extends RVFI with Direct Instruction Injection; DII is for instruction input and RVFI is for trace output. Randomized Testing of RISC-V CPUs using Direct

[3] Implementations must be extended with RVFI-DII instrumentation to participate in the TestRIG verification ecosystem, and Flute is listed among relevant RISC-V implementations. Randomized Testing of RISC-V CPUs using Direct

[4] The simple single-issue design of Piccolo and Flute enabled replacing the cache with a DII queue delivering one compressed or uncompressed instruction per cycle. Randomized Testing of RISC-V CPUs using Direct

[5] While adding RVFI-DII to Flute, researchers developed a sequence-ID design that carries IDs with instructions through the pipeline so Instruction Fetch can request each instruction ID from the DII sequence. Randomized Testing of RISC-V CPUs using Direct

[6] A more capable DII unit is available in RVFI-DII libraries and has been backported to Flute. Randomized Testing of RISC-V CPUs using Direct