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Flute

CodeArtifact WIKI v1 · 5/27/2026

Flute is a RISC-V processor implementation described as a 5-stage in-order pipeline processor implementing RV64. In the TestRIG/RVFI-DII context, its simple single-issue design allowed instruction-cache replacement with a Direct Instruction Injection queue, and RVFI-DII work on Flute led to a sequence-ID synchronization design later available in RVFI-DII libraries and backported to Flute.

Overview

Flute is a code artifact for a RISC-V processor implementation. The TestRIG paper identifies Flute as "a 5-stage in-order pipeline processor implementing RV64" and provides its repository as https://github.com/CTSRD-CHERI/Flute.[1]

Role in TestRIG and RVFI-DII

TestRIG is a randomized testing ecosystem for RISC-V CPUs that uses RVFI-DII instrumentation. RVFI-DII combines Direct Instruction Injection (DII) for instruction input with RVFI for trace output, supporting interactive verification.[2]

Within this ecosystem, implementations must be extended with RVFI-DII instrumentation to participate. The TestRIG paper lists Flute among RISC-V implementations considered in this context, alongside RVBS, Ibex, Piccolo, and Toooba.[3]

Direct Instruction Injection design

Flute is described as having a simple single-issue design, like Piccolo. This simplicity allowed the researchers to replace the instruction cache entirely with a DII queue that delivered one instruction per cycle, either compressed or uncompressed.[4]

The paper also describes a synchronization challenge for DII: canceled or dropped pipeline instructions must still correspond correctly to injected instructions, because RVFI-DII requires a single RVFI trace entry for each injected DII instruction. During RVFI-DII work on Flute, the researchers developed a design that attaches a sequence ID to each RVFI instruction and carries it with the program counter through the pipeline. Instruction Fetch requests each instruction ID from the DII sequence, allowing pipeline redirects to work naturally.[5]

A more capable DII unit based on this approach was made available in RVFI-DII libraries and was backported to Flute.[6]

Technical characterization

Key properties supported by the available evidence:

  • Implements RV64, the 64-bit RISC-V architecture profile.[1]
  • Uses a 5-stage in-order pipeline.[1]
  • Has a simple single-issue design in the context of DII instrumentation.[4]
  • Has been instrumented in the context of RVFI-DII and TestRIG experimentation.[5]

[1]: Flute is identified as a 5-stage in-order pipeline processor implementing RV64, with repository URL in the TestRIG paper. [2]: The TestRIG paper states that TestRIG extends RVFI with Direct Instruction Injection, where DII is for instruction input and RVFI is for trace output. [3]: The TestRIG paper lists Flute among implementations in the TestRIG context and states that implementations must be extended with RVFI-DII instrumentation to participate. [4]: The TestRIG paper states that the simple single-issue design of Piccolo and Flute enabled replacing the cache with a DII queue delivering one instruction every cycle. [5]: The TestRIG paper states that, while adding RVFI-DII to Flute, the researchers developed a sequence-ID design carried through the pipeline. [6]: The TestRIG paper states that the more capable DII unit is available in RVFI-DII libraries and has been backported to Flute.

LINKED ENTITIES

3 links
TestRIG EVALUATES
RISC-V IMPLEMENTS
RVFI-DII USES

CITATIONS

6 sources
6 citations
[1] Flute is a 5-stage in-order pipeline processor implementing RV64, and the paper provides its repository URL. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG extends RVFI with Direct Instruction Injection; DII is for instruction input and RVFI is for trace output. Randomized Testing of RISC-V CPUs using Direct
[3] Implementations must be extended with RVFI-DII instrumentation to participate in the TestRIG verification ecosystem, and Flute is listed among relevant RISC-V implementations. Randomized Testing of RISC-V CPUs using Direct
[4] The simple single-issue design of Piccolo and Flute enabled replacing the cache with a DII queue delivering one compressed or uncompressed instruction per cycle. Randomized Testing of RISC-V CPUs using Direct
[5] While adding RVFI-DII to Flute, researchers developed a sequence-ID design that carries IDs with instructions through the pipeline so Instruction Fetch can request each instruction ID from the DII sequence. Randomized Testing of RISC-V CPUs using Direct
[6] A more capable DII unit is available in RVFI-DII libraries and has been backported to Flute. Randomized Testing of RISC-V CPUs using Direct