Spike
Spike is a RISC-V instruction-set architecture (ISA) simulator. The evidence identifies it as the “Spike RISC-V ISA simulator” and also refers to it as the official RISC-V reference simulator. Two cited repository locations appear in the provided sources: https://github.com/riscv/riscv-isa-sim in the ISS-fuzzing paper and https://github.com/riscv-software-src/riscv-isa-sim in a later bibliography.
Role in ISS verification
In Verifying Instruction Set Simulators using Coverage-guided Fuzzing, Spike was one of three publicly available RISC-V instruction-set simulators used in a case study. The paper proposed applying coverage-guided fuzzing to ISS verification, adding a functional coverage metric to complement code coverage and a mutation procedure tailored to ISS verification. The implementation was built on the LLVM-based libFuzzer.
The paper reports that the approach was effective at maximizing most coverage metrics and found new errors in every considered ISS, including one error in Spike. In the evaluation table, the coverage-guided fuzzing run is listed as finding Spike issue S1; the RISC-V ISA tests and RISC-V Torture test generators are listed as finding no Spike issues in that table.
Evaluation result in the fuzzing study
The reported coverage-guided fuzzing run took 32,492 seconds and achieved 100% branch coverage in the instrumented ISS under test, along with 100% for the R1, R2, and R3 functional coverage columns shown in the table. For that run, the table reports all seven injected or tracked ISS-under-test errors [V1..V7], Spike issue S1, and Forvis issues H1,H2.