unordered floating-point reduction reference model

Technique

The unordered floating-point reduction reference model is a C reference model used in RISC-V vector accelerator verification to avoid false mismatches against Spike for unordered floating-point reductions. It implements the same reduction algorithm as the design under test and, on a matching result, injects that value back into Spike to prevent later execution divergence.

First seen 5/27/2026

Last seen 5/27/2026

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Overview

The unordered floating-point reduction reference model is an independent C reference model used during functional verification of a RISC-V vector accelerator. It was introduced for unordered floating-point reduction instructions whose behavior could produce mismatches against Spike even when the vector processing unit result was considered correct under the relevant rounding mode and reduction algorithm. [Citation: purpose-and-context]

Problem addressed

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Functional Verification of a RISC-V Vector Accelerator ← uses 95% 1e

The paper develops a custom C reference model for unordered floating-point reductions to avoid false mismatches with Spike.

spike compares with → 93% 1e

The unordered floating-point reduction reference model is used instead of Spike for non-deterministic reduction results.

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

spike COMPARES_WITH Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] purpose-and-context: The technique was introduced in a RISC-V vector accelerator verification setting to avoid false mismatches for unordered floating-point reductions. source

[2] false-positive-and-divergence-problem: Unordered floating-point reductions could cause mismatches even when correct under the rounding mode and algorithm, and Spike's retained differing register value could later cause additional mismatches. source

[3] c-model-and-comparison-flow: The verification flow created an independent C reference model for unordered reductions, implemented the same reduction algorithm as the DUT, compared VPU results against it instead of Spike, and injected the value into Spike when the model matched. source

[4] spike-integration: The verification environment used Spike to resume simulation to vector instructions, return reference results to UVM, read Spike memory, and force reduction results into Spike to avoid divergence. source

[5] spike-comparison-scope: The technique is used as an alternative comparison source for unordered reductions rather than as a wholesale replacement for Spike. source