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STIMSMITH

co-simulation testbench

CodeArtifact WIKI v1 · 5/30/2026

A co-simulation testbench for cross-level RISC-V processor verification that drives an RTL core and an ISS with an unrestricted instruction stream, uses a core adapter to observe completed RTL instructions, and applies instruction-stream matching plus randomized instruction generation to expose mismatches.

Overview

The co-simulation testbench is the verification setup described for cross-level testing of a pipelined 32-bit RISC-V core. Its purpose is to run an RTL core and an instruction set simulator (ISS) against an effectively endless, unrestricted instruction stream while detecting mismatches between the two models.

Main components

Core adapter

The testbench uses a core adapter to hide implementation-specific details of the RTL core and present a clean testing interface. The adapter observes internal signal changes, especially pipeline behavior, and notifies the test controller whenever the RTL core completes an instruction. It also preserves the correct order in the presence of illegal instructions and exposes RTL register values so that they can be compared with the ISS.

This adapter is needed because completion detection in a pipelined RTL core can require knowledge of pipeline timing, delays, and gaps caused by multi-cycle operations.

Instruction stream matching

The testbench cannot simply assume that the RTL core and ISS fetch in lockstep. The RTL core may prefetch multiple instructions, and prefetched instructions may later be discarded because of jumps or traps. Short jumps and traps can also make the RTL core fetch new instructions before the ISS has reached the same fetch point.

To handle this, the setup matches ISS fetches against a queue of pending instructions delivered to the RTL core. If a matching instruction is found, it is returned to the ISS; otherwise, the testbench reports a mismatch because the ISS attempted to fetch an instruction that had not been delivered to the RTL core. The approach deliberately avoids feeding the RTL core's completed instruction sequence directly into the ISS, because doing so would rely on correct instruction propagation inside the RTL core, which is the design under test.

Instruction stream generator

The instruction stream generator provides the testbench with unrestricted instruction input. Its baseline behavior is to fully randomize generated instructions. The paper then describes several guidance mechanisms:

  • injecting a random valid opcode into an otherwise randomized 32-bit word, to create a legal instruction while leaving fields randomized;
  • applying field-mutation rules derived from RISC-V instruction formats;
  • injecting special immediate values such as MIN, -1, 0, 1, and MAX;
  • mutating register fields, for example setting RD to zero, making RD equal to RS1 and/or RS2, or making RS1 match RS2;
  • mutating a CSR selector field to a supported CSR;
  • occasionally generating fixed-length instruction sequences rather than only independent instructions.

The algorithm shown in the paper starts a new instruction sequence with 1% probability, injects a random valid opcode with 98% probability, and applies a random field mutation with 20% probability.

Role in the verification flow

Together, the core adapter, instruction-stream matching, and guided instruction generation allow the co-simulation setup to compare RTL behavior against the ISS without constraining the generated program stream to simple lockstep execution. This is central to the cross-level testing approach introduced in the RISC-V processor verification case study.

LINKED ENTITIES

7 links
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study INTRODUCES
Co-Simulation IMPLEMENTS
SystemC USES
TLM (Transaction Level Modeling) USES
core adapter USES
test controller USES
instruction generation algorithm PART_OF

CITATIONS

8 sources
8 citations
[1] The co-simulation testbench is part of a cross-level RISC-V processor verification setup that runs an RTL core and ISS with an unrestricted instruction stream. Efficient Cross-Level Testing for
[2] The core adapter hides core implementation details, observes internal pipeline-related signal changes, notifies the test controller on completed instructions, preserves order for illegal instructions, and provides RTL register access for comparison with the ISS. Efficient Cross-Level Testing for
[3] Instruction stream matching is needed because RTL prefetching, jumps, and traps can make the RTL core and ISS fetch different instruction sequences or fetch them at different times. Efficient Cross-Level Testing for
[4] The matching mechanism compares ISS fetch requests with a queue of pending instructions delivered to the RTL core and reports a mismatch if the ISS fetches an instruction not delivered to the RTL core. Efficient Cross-Level Testing for
[5] The setup avoids feeding completed RTL instructions directly to the ISS because doing so would rely on correct instruction propagation inside the RTL core under test. Efficient Cross-Level Testing for
[6] The instruction generator baseline fully randomizes generated instructions, and guidance mechanisms include opcode injection, field mutation, and instruction-sequence generation. Efficient Cross-Level Testing for
[7] Field mutation rules include special immediate values, register-field relationships such as RD equals RS1 or RS2, RD set to zero, RS1 matching RS2, and mutation of CSR selectors to supported CSRs. Efficient Cross-Level Testing for
[8] The algorithm shown in the paper starts a sequence with 1% probability, injects a random valid opcode with 98% probability, and applies a field mutation with 20% probability. Efficient Cross-Level Testing for