bfloat16
Conceptbfloat16 is a 16-bit floating-point machine number format proposed as an alternative to IEEE 754, used in deep learning hardware acceleration and in formal hardware synthesis toolchains.
First seen 6/8/2026
Last seen 6/8/2026
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Overview
bfloat16 is a 16-bit floating-point number format. It has been proposed alongside other alternative machine number formats, such as posit and takum, as a replacement or complement to the IEEE 754 standard. It is also distinct from OCP 8-bit floating point (OFP8) types (E4M3 and E5M2), which are 8-bit extensions of IEEE 754 with slight deviations from the standard.
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2 connectionsThe paper evaluates synthesis of floating-point rewrite rules using bfloat16.
bfloat16 is a floating-point format used in the CGRA processing elements.
CITATIONS
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[1] bfloat16 is a 16-bit floating-point number format proposed as an alternative to IEEE 754, alongside posit and takum and distinct from OFP8 (E4M3, E5M2) 8-bit extensions. Integer Representations in IEEE 754, Posit, and Takum Arithmetics
[2] bfloat16 generally underperforms in integral representation compared to OFP8, posits, and takums. Integer Representations in IEEE 754, Posit, and Takum Arithmetics
[3] PE-F adds 16-bit floating point (bfloat16) addition and multiplication to a base 16-bit processing element used in CGRA design-space exploration. Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
[4] The study synthesizes rewrite rules for CoreIR's 16-bit integer, Boolean, and bfloat16 floating-point instructions; floating-point rules for PE-F are found within 1.2 seconds. Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
[5] TATAA uses bfloat16 floating-point arithmetic to approximate the non-linear layers of transformer models and int8 for quantized linear layer operations. TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
[6] TATAA's transformable arithmetic architecture supports int8 and bfloat16 with minimal overhead, switching between systolic array mode (int8) and SIMD mode (bfloat16). TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
[7] TATAA's mixed-precision design incurs only 0.14% to 1.16% accuracy drop versus pre-trained single-precision transformer models across vision, language, and generative text applications. TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
[8] The TATAA prototype on the Alveo U280 FPGA achieves 2935.2 GOPS on linear layers and up to 189.5 GFLOPS for non-linear operations. TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture