Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs
PaperFirst seen 8/15/2026
Last seen 8/15/2026
Evidence 12 chunks
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28 connectionsThe paper varies mutation count as a verification parameter.
The paper uses a virtual prototype as the golden reference model in the cross-level setup.
The paper evaluates functional coverage as one of the key metrics.
The paper examines coverage saturation behavior across different metrics and parameters.
The paper evaluates value coverage of registers and immediates in the instruction stream.
The paper evaluates register file access patterns in the generated instruction sequences.
The paper introduces open-source mutation generation scripts for injecting bugs into RTL designs.
The paper evaluates RTL code coverage as one of the key metrics.
The paper uses riscv-dv as the CRV instruction generation framework.
The paper uses mutation testing as a proxy for bug-finding effectiveness.
The paper targets RISC-V ISA as the instruction set for the verified CPU.
The paper evaluates mutation coverage as one of the key metrics.
The paper uses the RTL mutation engine to inject mutations into the DUV.
The paper uses a commercial RTL simulator for simulation-based coverage measurement.
The paper varies instruction sequence length as a verification parameter.
The paper varies mutation location as a verification parameter.
The paper uses multiple CRV strategies to generate different types of instruction sequences.
The paper is authored by Luca Müller.
The paper is authored by Rolf Drechsler.
The paper employs Constrained Random Verification as its primary verification methodology.
The paper uses cross-level verification in a VP-RTL setup.
The paper uses MicroRV32 as the RISC-V RTL SoC implementation under verification.
The paper uses RISC-V VP as the virtual prototype counterpart for cross-level verification.
The paper uses execution trace comparison between VP and RTL to detect mismatches.
The paper mentions FORCE-RISCV as an alternative instruction generation tool.
The paper mentions RISC-V Torture Test as an alternative instruction generation tool.
The paper mentions feedback-based methods as future work to improve CRV strategies.
The paper is authored by Sallar Ahmadi-Pour.