ALU

Concept

An Arithmetic Logic Unit (ALU) is a fundamental processor submodule that performs arithmetic and logical operations on operands. The evidence covers ALUs in three distinct contexts: as a block within RISC-V processor cores (especially the Ibex core, where it forms an instruction category covering reg/reg and reg/imm instructions other than MUL/DIV) that is a primary target of functional verification using UVM-based simulation, mutation-based fault injection, and formal methods; as the basis of heterogeneous ALU architectures that route operations to differently sized ALUs for energy efficiency; and as specialized implementations such as superconducting ERSFQ designs.

First seen 5/27/2026

Last seen 8/27/2026

Evidence 8 chunks

Wiki v4

WIKI

ALU

Definition and Role

An Arithmetic Logic Unit (ALU) is a fundamental processor submodule that performs arithmetic and logical operations on operands. The provided evidence describes ALUs in several distinct contexts: as a target of functional verification in RISC-V processor designs [C1][C2][C3][C4][C7][C8], as the object of mutation-based verification studies with quantitative coverage metrics [C7][C8], as the basis of heterogeneous architectures that route operations to differently sized ALUs for energy efficiency [C5], as a defined instruction category inside the Ibex RISC-V core coverage plan [C9], and as specialized implementations such as superconducting single-flux-quantum (SFQ) designs [C6].

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

4 connections

Processor Verification ← uses 85% 1e

ALU submodules must be formally verified before integration to avoid discovering bugs late.

RISC-V part of → 97% 1e

The ALU is a key execution block of the RISC-V processor core.

MicroRV32 part of → 100% 1e

MicroRV32 contains an ALU as one of its submodules.

ALU Instruction Category ← uses 1e

ALU Instruction Category uses the ALU for computation.

LINKED ENTITIES

1 links

ALU Instruction Category USES Extracted graph relationship

CITATIONS

13 sources

13 citations — click to expand

[1] An ALU is a fundamental processor submodule that performs arithmetic and logical operations on operands. Verification Of Risc-V Core Blocks Using Uvm

[2] In a RISC-V core the ALU sits inside the Execute Unit, alongside optional multiplier/divider blocks, downstream of the Instruction Fetch and Decode Units. Verification Of Risc-V Core Blocks Using Uvm

[3] In the Ibex coverage plan, the ALU instruction category is defined at the ID/EX stage as all reg/reg and reg/imm instructions with opcodes 7'b0010011 (OPCODE_OP_IMM) or 7'b0110011 (OPCODE_OP) excluding the MUL* and DIV* families (RV32M); ADD and SUB share this category because they differ only in the ALU operation. Coverage Plan — Ibex Documentation

[4] Targeted UVM test scenarios for the ALU include arithmetic and logical operations such as ADD, SUB, AND, and OR; functional coverage points cover ALU operation types, instruction types, and operand combinations. Verification Of Risc-V Core Blocks Using Uvm

[5] The ALU/LSU pair is exercised through constrained-random RISC-V instructions of all formats and corner cases, with monitors tracking register updates, memory accesses, and exception events; the scoreboard compares DUT results against an architectural reference model such as Spike or a custom ISA model. Verification Of Risc-V Core Blocks Using Uvm

[6] A documented UVM project reports that all targeted units — including the Execute Unit containing the ALU — were verified against the RISC-V specification using constrained-random testing, assertions, and a reference model, with functional and assertion coverage goals achieved and corner-case bugs identified and resolved. Verification Of Risc-V Core Blocks Using Uvm

[7] Cross-level mutation studies on a RISC-V core treat the ALU as one of the targeted submodules (alongside Control, Fetch, Decode, and MulDiv) for fault injection, with mutations injected via Yosys-based tooling that can flip bits, replace bits with constants, or alter logic operations in expressions; ineffective mutations are filtered out before cross-level simulation against a virtual prototype. Exploring the Parameter Space for Constrained Random ...

[8] Module-based mutation breakdown (PV er1 × PV er3) for the ALU: 1963/2500 (78.5%) mutations killed at 100 instructions with 42.9% relative functional coverage; 2086/2500 (83.4%) killed at 1000 instructions with 46.4% functional coverage; 2217/2500 (88.7%) killed at 10000 instructions with 47.8% functional coverage; RTL branch/statement/toggle coverage stays roughly in the 78–86% / 70% ranges across these instruction counts. Exploring the Parameter Space for Constrained Random ...

[9] Module-level killed-mutation rates for the same study: Control 44.8%/58.6%/85.9%; Decode 76.7%/63.1%/62.8%; Fetch (1245 mutations) 95.4%/95.6%/96.9%; MulDiv 84.6%/89.0%/95.1%; full Core 54.3%/54.4%/69.4% — at 100, 1000, and 10000 instructions respectively. Exploring the Parameter Space for Constrained Random ...

[10] A heterogeneous ALU system is proposed to achieve energy-saving and potentially performance-improving benefits without sacrificing generality, by routing ALU operations to properly sized ALUs, with energy-constrained modes routing operations to smaller ALUs for large energy savings; the evaluation examines scaling ripple carry adders with input operand size-based and energy constraint-based routing controls. Heterogeneous ALU Architecture -- Power Aware System

[11] A parallel 8-bit ERSFQ ALU employs wave-pipelined instruction execution and a modular bit-slice architecture easily extendable to any number of bits; the instruction set consists of 14 arithmetical and logical instructions, and the design has been simulated for operation up to a 10 GHz clock rate at the 10-kA/cm² process. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[12] The 8-bit ERSFQ ALU comprises 6840 Josephson junctions, fabricated with the MIT Lincoln Lab 10-kA/cm² SFQ5ee process featuring eight Nb wiring layers and a high-kinetic-inductance layer needed for ERSFQ technology. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[13] Bias margins for the 8-bit ERSFQ ALU were evaluated at low and high frequency: at low frequency clock and all instruction propagation through the ALU were observed with bias margins of ±11% and ±9%, respectively, and the ALU exhibited correct functionality for all arithmetical and logical instructions with ±6% bias margins; the 8-bit ALU was tested for all instructions up to 2.8 GHz clock frequency, embedded into a shift-register-based high-frequency testbed with an on-chip clock generator. ERSFQ 8-bit Parallel Arithmetic Logic Unit