ALU

Concept

An Arithmetic Logic Unit (ALU) is a processor submodule that performs arithmetic and logical operations. In RISC-V designs the ALU sits inside the Execute Unit and is a primary target of formal and UVM-based functional verification; the evidence also covers heterogeneous ALU architectures that route operations to differently sized ALUs for energy savings, and specialized implementations such as superconducting ERSFQ ALUs.

First seen 5/27/2026

Last seen 7/6/2026

Evidence 5 chunks

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ALU

Definition and Role

An Arithmetic Logic Unit (ALU) is a fundamental processor submodule that performs arithmetic and logical operations on operands. The provided evidence describes ALUs in several distinct contexts: as a target of functional verification in RISC-V processor designs [C1][C2][C3][C4], as the basis of heterogeneous architectures that route operations to differently sized ALUs for energy efficiency [C5], and as specialized implementations such as superconducting single-flux-quantum (SFQ) designs [C6].

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RELATIONSHIPS

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Processor Verification ← uses 85% 1e

ALU submodules must be formally verified before integration to avoid discovering bugs late.

RISC-V part of → 97% 1e

The ALU is a key execution block of the RISC-V processor core.

LINKED ENTITIES

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RISC-V PART_OF Extracted graph relationship

CITATIONS

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8 citations — click to expand

[1] Discovering an ALU bug only when booting Linux would be a difficult experience, motivating early ALU verification; formal verification exhaustively explores ALU input combinations against ISA-specified behavior expressed as SystemVerilog assertions, while simulation is needed to validate all modules and SoC integration. RISC-V Microarchitecture Verification Approaches

[2] Teams validate ALU behavior against a reference model, and RISC-V custom instructions expand verification scope, requiring re-verification especially when changes touch pipeline control, ALU conflicts, cache behavior, or load-store paths. RISC-V Microarchitecture Verification Approaches

[3] Verification is never truly complete; a practical goal is to reduce residual risk to a manageable level, and coverage alone is insufficient because instruction sequences and dynamic pipeline events also matter. RISC-V Microarchitecture Verification Approaches

[4] A UVM-based verification project for RISC-V core blocks explicitly lists the ALU (within the Execute Unit, alongside MUL/DIV) as a key block to verify individually against the RISC-V specification using constrained-random testing, assertions, and a reference model. Verification Of Risc-V Core Blocks Using Uvm

[5] UVM test cases for the ALU target operations such as ADD, SUB, AND, and OR, with coverage points on ALU operation types, instruction types, and operand combinations, driven through constrained-random RISC-V instruction streams compared against an ISA reference model. Verification Of Risc-V Core Blocks Using Uvm

[6] A documented UVM project reports that all targeted RISC-V units — including the Execute Unit containing the ALU — were verified, achieving functional and assertion coverage goals and identifying corner-case bugs. Verification Of Risc-V Core Blocks Using Uvm

[7] A heterogeneous ALU architecture can route operations to properly sized ALUs for energy and performance benefits without sacrificing generality, with energy-constrained modes routing to smaller ALUs; the proposal is evaluated using scaled ripple carry adders with operand-size and energy-constraint-based routing controls. Heterogeneous ALU Architecture -- Power Aware System

[8] A parallel 8-bit ERSFQ ALU using wave pipelining and a modular bit-slice architecture supports 14 arithmetical and logical instructions and is designed for up to 10 GHz operation; the fabricated 8-bit version uses 6840 Josephson junctions in MIT Lincoln Lab's 10-kA/cm² SFQ5ee process, with measured bias margins of ±11% (clock) and ±9% (instruction propagation) at low frequency, ±6% for correct functionality of all instructions, and verified operation up to 2.8 GHz. ERSFQ 8-bit Parallel Arithmetic Logic Unit