:FLE
ISAThe Zfa extension adds a quiet NaN-handling variant of floating-point less-than-or-equal compare; FLE.S/.D/.H derive from RISC-V Zfa via sail-riscv commit f2d8e1b9.
First seen 9/27/2026
Last seen 9/27/2026
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:FLE
FLE is a RISC-V floating-point instruction. The instructions FLE.H, FLE.S and FLE.D (the latter shortened to FLE for the single-precision case) perform a floating-point less-than-or-equal comparison.
Evidence from sail-riscv commit f2d8e1b9 (the Zfa extension patch) shows that quiet-NaN-handling siblings FLEQ.H, FLEQ.S, FLEQ.D and the LTQ family (FLTQ.H, FLTQ.S, FLTQ.D) are added by Zfa.''
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3 connectionsFLEQ is defined like FLE but quiet NaNs do not raise invalid operation.
FLEQ is defined like FLE but quiet NaNs do not raise invalid operation.
FLEQ is defined like FLE but quiet NaNs do not raise invalid operation.
LINKED ENTITIES
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[1] FLEQ.H, FLEQ.S, FLEQ.D are added by the sail-riscv commit f2d8e1b9 introducing Zfa infrastructure plus .H/.S/.D instruction support. sail-riscv commit f2d8e1b9 ('Add Zfa extension support (excl. quad-precision)')
[2] FLEQ and FLTQ instructions are defined like the FLE and FLT instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set. sail-riscv commit f2d8e1b9 ('Add Zfa extension support (excl. quad-precision)')