FLEQ.D

ISA

FLEQ.D is a floating-point comparison instruction introduced as part of the RISC-V Zfa extension. It compares double-precision (D) floating-point values, returning a result based on whether the first operand is less than or equal to the second, while differing from the existing FLE.D instruction in its NaN-handling behavior: quiet NaN inputs do not set the invalid operation exception flag.

First seen 9/27/2026

Last seen 9/27/2026

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Overview

FLEQ.D is a floating-point comparison instruction in the RISC-V ISA that operates on double-precision (D) floating-point values. It is one of the FLEQ-family instructions (FLEQ.[HSD]) introduced by the Zfa extension, alongside its sibling FLTQ.[HSD].

Semantics

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NEIGHBORHOOD

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RELATIONSHIPS

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Zfa part of → 90% 1e

Zfa adds the FLEQ.D instruction.

sail-riscv ← implements 93% 1e

sail-riscv supports FLEQ.D.

FLE derived from → 92% 1e

FLEQ is defined like FLE but quiet NaNs do not raise invalid operation.

LINKED ENTITIES

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sail-riscv IMPLEMENTS Extracted graph relationship

Zfa PART_OF Extracted graph relationship

FLE DERIVED_FROM Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] FLEQ.D is part of the Zfa extension and is implemented as part of the FLEQ.[HSD] / FLTQ.[HSD] instruction family. Commits · riscv/sail-riscv (Zfa support commit f2d8e1b9)

[2] FLEQ is defined like FLE, except that quiet NaN inputs do not cause the invalid operation exception flag to be set. Commits · riscv/sail-riscv (Zfa support commit f2d8e1b9)

[3] sail-riscv commit f2d8e1b9 adds Zfa infrastructure (e.g., existence macro) and implements the Zfa instructions including FLEQ.[HSD] and FLTQ.[HSD]. Commits · riscv/sail-riscv (Zfa support commit f2d8e1b9)