sail-riscv

CodeArtifact

First seen 9/27/2026

Last seen 9/27/2026

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RISC-V targets ISA → 80% 1e

The Sail RISC-V model (sail-riscv) targets the RISC-V ISA.

Zfa implements → 95% 1e

This commit adds infrastructure and instruction support for the Zfa extension in sail-riscv.

FLI.H implements → 93% 1e

sail-riscv adds support for the FLI.H instruction as part of Zfa.

FLI.S implements → 93% 1e

sail-riscv adds support for the FLI.S instruction as part of Zfa.

FLI.D implements → 93% 1e

sail-riscv adds support for the FLI.D instruction as part of Zfa.

FMINM.H implements → 93% 1e

sail-riscv supports FMINM.H.

FMINM.S implements → 93% 1e

sail-riscv supports FMINM.S.

FMINM.D implements → 93% 1e

sail-riscv supports FMINM.D.

FMAXM.H implements → 93% 1e

sail-riscv supports FMAXM.H.

FMAXM.S implements → 93% 1e

sail-riscv supports FMAXM.S.

FMAXM.D implements → 93% 1e

sail-riscv supports FMAXM.D.

FROUND.H implements → 93% 1e

sail-riscv supports FROUND.H.

FROUND.S implements → 93% 1e

sail-riscv supports FROUND.S.

FROUND.D implements → 93% 1e

sail-riscv supports FROUND.D.

FROUNDNX.H implements → 93% 1e

sail-riscv supports FROUNDNX.H.

FROUNDNX.S implements → 93% 1e

sail-riscv supports FROUNDNX.S.

FROUNDNX.D implements → 93% 1e

sail-riscv supports FROUNDNX.D.

FMVH.X.D implements → 95% 1e

sail-riscv supports FMVH.X.D.

FMVP.D.X implements → 95% 1e

sail-riscv supports FMVP.D.X.

FLEQ.H implements → 93% 1e

sail-riscv supports FLEQ.H.

FLEQ.S implements → 93% 1e

sail-riscv supports FLEQ.S.

FLEQ.D implements → 93% 1e

sail-riscv supports FLEQ.D.

FLTQ.H implements → 93% 1e

sail-riscv supports FLTQ.H.

FLTQ.S implements → 93% 1e

sail-riscv supports FLTQ.S.

FLTQ.D implements → 93% 1e

sail-riscv supports FLTQ.D.

FCVTMOD.W.D implements → 95% 1e

sail-riscv supports FCVTMOD.W.D.