FCVTMOD.W.D
ISAFCVTMOD.W.D is a RISC-V floating-point instruction that converts a double-precision floating-point value to a signed 32-bit integer, defined as part of the Zfa extension. It is derived from FCVT.W.D but differs in its rounding behavior and handling of exceptional inputs.
First seen 9/27/2026
Last seen 9/27/2026
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Overview
FCVTMOD.W.D is a floating-point-to-integer conversion instruction in the RISC-V ISA. It is part of the Zfa extension for additional floating-point operations and is implemented in the sail-riscv reference model.
Semantics
NEIGHBORHOOD
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3 connectionsZfa adds the FCVTMOD.W.D instruction.
sail-riscv supports FCVTMOD.W.D.
FCVTMOD.W.D is defined similarly to FCVT.W.D with specified rounding and saturation differences.
CITATIONS
4 sources4 citations — click to collapse
[1] FCVTMOD.W.D is part of the Zfa extension for RISC-V floating-point instructions. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[2] FCVTMOD.W.D always rounds towards zero, takes bits 31:0 from the rounded unbounded two's complement result, sign-extends to XLEN bits, and converts positive infinity, negative infinity, and NaN to zero. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[3] FCVTMOD.W.D is derived from FCVT.W.D with differences in rounding and exceptional input handling. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[4] sail-riscv added Zfa extension support (excluding quad-precision) in commit f2d8e1b9, implementing FCVTMOD.W.D among other instructions. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9