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FCVTMOD.W.D

ISA WIKI v1 · 9/27/2026

FCVTMOD.W.D is a RISC-V floating-point instruction that converts a double-precision floating-point value to a signed 32-bit integer, defined as part of the Zfa extension. It is derived from FCVT.W.D but differs in its rounding behavior and handling of exceptional inputs.

Overview

FCVTMOD.W.D is a floating-point-to-integer conversion instruction in the RISC-V ISA. It is part of the Zfa extension for additional floating-point operations and is implemented in the sail-riscv reference model.

Semantics

The FCVTMOD.W.D instruction is defined similarly to FCVT.W.D, with the following differences:

  • Rounding mode: FCVTMOD.W.D always rounds towards zero.
  • Result truncation: Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register rd.
  • Exceptional inputs: Positive infinity, negative infinity, and NaN are converted to zero.

Zfa Extension Context

FCVTMOD.W.D was introduced alongside other Zfa instructions, including:

  • FLI.[HSD]
  • FMINM.[HSD] and FMAXM.[HSD]
  • FROUND.[HSD] and FROUNDNX.[HSD]
  • FMVH.X.D and FMVP.D.X
  • FLEQ.[HSD] and FLTQ.[HSD]

Quad-precision floating-point variants are excluded from this initial Zfa implementation.

Implementation

The sail-riscv formal specification model added Zfa extension support (excluding quad-precision) in commit f2d8e1b9, which includes the FCVTMOD.W.D instruction along with the necessary infrastructure (such as the Zfa existence macro).

Relationships

LINKED ENTITIES

3 links
Zfa PART_OF
sail-riscv IMPLEMENTS
FCVT.W.D DERIVED_FROM

CITATIONS

4 sources
4 citations
[1] FCVTMOD.W.D is part of the Zfa extension for RISC-V floating-point instructions. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[2] FCVTMOD.W.D always rounds towards zero, takes bits 31:0 from the rounded unbounded two's complement result, sign-extends to XLEN bits, and converts positive infinity, negative infinity, and NaN to zero. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[3] FCVTMOD.W.D is derived from FCVT.W.D with differences in rounding and exceptional input handling. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9
[4] sail-riscv added Zfa extension support (excluding quad-precision) in commit f2d8e1b9, implementing FCVTMOD.W.D among other instructions. Add Zfa extension support (excl. quad-precision) — sail-riscv commit f2d8e1b9