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FCVT.W.D

ISA

FCVT.W.D is an RISC-V floating-point-to-integer conversion instruction. It converts a double-precision floating-point value to a 32-bit signed integer in an integer register. The instruction is referenced as the baseline for the Zfa extension's FCVTMOD.W.D, which modifies its rounding and overflow behavior.

First seen 9/27/2026
Last seen 9/27/2026
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FCVT.W.D

Overview

FCVT.W.D is a RISC-V single-precision floating-point instruction that converts a double-precision floating-point value to a 32-bit signed integer, writing the result into integer register rd.

(Editor's note: the canonical mnemonic FCVT.W.D follows the RISC-V FCVT family convention of "convert from floating-point to integer". The remainder of this article records what the available evidence supports.)

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RELATIONSHIPS

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FCVTMOD.W.D ← derived from 95% 1e
FCVTMOD.W.D is defined similarly to FCVT.W.D with specified rounding and saturation differences.

CITATIONS

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[1] FCVTMOD.W.D is defined similarly to FCVT.W.D but always rounds towards zero, sign-extends bits 31:0 of the unbounded two's complement result to XLEN bits, and converts positive infinity, negative infinity, and NaN to zero. Commits · 9b477812019a78510ebc7f4c7b7efbf378e64a42 · github ...