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FCVT.W.D

ISA WIKI v1 · 9/27/2026

FCVT.W.D is an RISC-V floating-point-to-integer conversion instruction. It converts a double-precision floating-point value to a 32-bit signed integer in an integer register. The instruction is referenced as the baseline for the Zfa extension's FCVTMOD.W.D, which modifies its rounding and overflow behavior.

FCVT.W.D

Overview

FCVT.W.D is a RISC-V single-precision floating-point instruction that converts a double-precision floating-point value to a 32-bit signed integer, writing the result into integer register rd.

(Editor's note: the canonical mnemonic FCVT.W.D follows the RISC-V FCVT family convention of "convert from floating-point to integer". The remainder of this article records what the available evidence supports.)

Role in the Zfa Extension

The Zfa extension for RISC-V introduces an instruction, FCVTMOD.W.D, defined similarly to FCVT.W.D, with the following documented differences:

  • FCVTMOD.W.D always rounds towards zero.
  • Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register rd.
  • Positive infinity, negative infinity, and NaN are converted to zero.

The FCVTMOD.W.D instruction was added to the sail-riscv model as part of the commit that introduced Zfa support (excluding quad-precision), along with several other Zfa instructions such as FLI.[HSD], FMINM.[HSD], FMAXM.[HSD], FROUND.[HSD], FROUNDNX.[HSD], FMVH.X.D, FMVP.D.X, FLEQ.[HSD], and FLTQ.[HSD].

See Also

  • FCVTMOD.W.D — derived from FCVT.W.D; rounds towards zero, treats infinities and NaN as zero, and sign-extends the 32-bit two's complement result to XLEN bits.

References

  • sail-riscv commit f2d8e1b9 (commit 9b477812019a78510ebc7f4c7b7efbf378e64a42), which adds Zfa extension support (excluding quad-precision) and contains the definition of FCVTMOD.W.D relative to FCVT.W.D.

LINKED ENTITIES

1 links
FCVTMOD.W.D DERIVED_FROM

CITATIONS

1 sources
1 citations
[1] FCVTMOD.W.D is defined similarly to FCVT.W.D but always rounds towards zero, sign-extends bits 31:0 of the unbounded two's complement result to XLEN bits, and converts positive infinity, negative infinity, and NaN to zero. Commits · 9b477812019a78510ebc7f4c7b7efbf378e64a42 · github ...