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FLEQ.D

ISA WIKI v1 · 9/27/2026

FLEQ.D is a floating-point comparison instruction introduced as part of the RISC-V Zfa extension. It compares double-precision (D) floating-point values, returning a result based on whether the first operand is less than or equal to the second, while differing from the existing FLE.D instruction in its NaN-handling behavior: quiet NaN inputs do not set the invalid operation exception flag.

Overview

FLEQ.D is a floating-point comparison instruction in the RISC-V ISA that operates on double-precision (D) floating-point values. It is one of the FLEQ-family instructions (FLEQ.[HSD]) introduced by the Zfa extension, alongside its sibling FLTQ.[HSD].

Semantics

FLEQ.D performs a less-than-or-equal comparison on two double-precision floating-point operands. It is defined analogously to the existing FLE.D instruction, except that quiet NaN inputs do not cause the invalid operation exception flag to be set (as reported for the FLEQ family in the Zfa commit message on sail-riscv).

Extension and Derivation

  • FLEQ.D is part of the Zfa extension, an addition to the RISC-V floating-point ISA.
  • The Zfa extension itself is derived from and extends the base FLE family of floating-point comparison semantics; FLEQ.D specifically parallels FLE.D with relaxed NaN-exception behavior.

Implementation in sail-riscv

The sail-riscv formal model added Zfa support (excluding quad-precision) in commit f2d8e1b9 on the riscv/sail-riscv repository. That commit bundles the implementation of FLEQ.[HSD] and FLTQ.[HSD] together with the other Zfa instructions:

  • FLI.[HSD]
  • FMINM.[HSD] / FMAXM.[HSD]
  • FROUND.[HSD] / FROUNDNX.[HSD]
  • FMVH.X.D / FMVP.D.X
  • FLEQ.[HSD] / FLTQ.[HSD]
  • FCVTMOD.W.D

The commit also establishes the Zfa infrastructure (e.g., existence macro) on which FLEQ.D depends.

See also

  • FLE — base floating-point less-than-or-equal family from which FLEQ.D's semantics are derived.
  • Zfa — the extension that defines FLEQ.D.
  • sail-riscv — the formal RISC-V model that implements FLEQ.D.

LINKED ENTITIES

3 links
sail-riscv IMPLEMENTS
Zfa PART_OF
FLE DERIVED_FROM

CITATIONS

3 sources
3 citations
[1] FLEQ.D is part of the Zfa extension and is implemented as part of the FLEQ.[HSD] / FLTQ.[HSD] instruction family. Commits · riscv/sail-riscv (Zfa support commit f2d8e1b9)
[2] FLEQ is defined like FLE, except that quiet NaN inputs do not cause the invalid operation exception flag to be set. Commits · riscv/sail-riscv (Zfa support commit f2d8e1b9)
[3] sail-riscv commit f2d8e1b9 adds Zfa infrastructure (e.g., existence macro) and implements the Zfa instructions including FLEQ.[HSD] and FLTQ.[HSD]. Commits · riscv/sail-riscv (Zfa support commit f2d8e1b9)