UVM Verification of RISC-V Instruction Set (ICAECA 2024)

Paper

First seen 9/21/2026

Last seen 9/21/2026

Evidence 3 chunks

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RISC-V targets ISA → 94% 1e

It presents a UVM testbench focused on verifying RISC-V instructions.

UVM uses → 92% 1e

Its methodology is based on a complete UVM testbench.

Stimuli are generated in a constrained-random fashion for ISA verification.