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STIMSMITH

Stateful Symbolic Simulation

Technique
First seen 8/25/2026
Last seen 8/25/2026
Evidence 3 chunks

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RELATIONSHIPS

5 connections
Advanced Virtual Prototyping for Cyber-Physical Systems Using RISC-V ← uses 100% 1e
The paper presents stateful symbolic simulation for SystemC verification
Symbolic Execution uses → 100% 1e
Stateful symbolic simulation integrates symbolic execution as one of its core techniques
Partial Order Reduction (POR) uses → 100% 1e
Stateful symbolic simulation uses POR to prune redundant scheduling sequences
State Subsumption Reduction (SSR) uses → 100% 1e
Stateful symbolic simulation uses SSR to detect exploration cycles
Intermediate Verification Language (IVL) uses → 100% 1e
Stateful symbolic simulation is based on the IVL