Advanced Virtual Prototyping for Cyber-Physical Systems Using RISC-V
PaperFirst seen 8/25/2026
Last seen 8/25/2026
Evidence 11 chunks
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21 connectionsThe paper presents coverage-guided fuzzing as one of the VP-based verification approaches
The paper presents the RISC-V VP as its main contribution
The paper evaluates and verifies the RISC-V VP
The paper compares VPs with QEMU as a high-speed functional simulator
The paper discusses and applies compliance testing for RISC-V
The paper uses ISS as reference model in cross-level verification
The paper presents cross-level co-simulation for VP/RTL verification
The paper discusses formal verification techniques for SystemC designs
The paper is authored by Vladimir Herdt
The paper/authors introduced the IVL as a formal intermediate representation for SystemC
The paper uses mutation testing for compliance test-suite generation
The paper uses a signature-based test infrastructure for VP and compliance testing
The paper focuses on virtual prototyping for cyber-physical systems
The paper mentions HLS as an important building block in the design flow
The paper presents VP-based embedded SW verification approaches
The paper presents stateful symbolic simulation for SystemC verification
The paper is co-authored by Rolf Drechsler
The paper is affiliated with the University of Bremen
The paper is affiliated with DFKI GmbH
The paper presents concolic testing as one of the VP-based verification approaches
The paper presents DIFT as one of the VP-based verification approaches