Architecture-aware stimulus generation

Technique

Architecture-aware stimulus generation is a RISC-V processor verification technique that produces randomized instruction sequences constrained by the target Instruction Set Architecture (ISA), enabling compliance-driven, high-coverage testing of cores such as Ibex. The approach is implemented by tools like riscv-dv and underpins the Instruction Stream Generator (ISG) component of such frameworks.

First seen 9/27/2026

Last seen 9/27/2026

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Architecture-aware stimulus generation

Architecture-aware stimulus generation is a functional verification technique used in RISC-V processor design validation. Rather than relying on fully unconstrained random programs, the technique generates random instructions whose encoding and behavior are constrained to be legal and meaningful with respect to the targeted RISC-V Instruction Set Architecture. This allows the verification environment to focus exploration on sequences the DUT can actually execute, while still retaining the coverage benefits of randomness.

Context and motivation

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RELATIONSHIPS

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riscv-dv ← implements 76% 2e

The ISG’s stated goals include architecture awareness; as the ISG at [4], riscv-dv implements architecture-aware stimulus generation.

Instruction Stream Generator (ISG) part of → 90% 1e

Architecture-aware stimulus generation is identified as a key feature of the ISG.

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riscv-dv IMPLEMENTS Extracted graph relationship

Instruction Stream Generator (ISG) PART_OF Extracted graph relationship

CITATIONS

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[1] Architecture-aware stimulus generation uses random instructions whose encoding is constrained to be legal with respect to the targeted RISC-V ISA, enabling compliance-driven testing of cores such as Ibex. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification

[2] riscv-dv (github.com/google/riscv-dv) is an open-source RISC-V instruction stream generator that implements architecture-aware stimulus generation. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification

[3] The verification flow that uses architecture-aware stimulus generation is typically deployed inside UVM testbenches and relies on ISS-based reference models, such as those exposed via the Open Virtual Platforms (OVP) API, for self-checking. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification

[4] The RISC-V specifications and the RISC-V compliance test suite (riscv-compliance) are foundational references for ensuring generated stimulus respects the architecture. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification