Design Under Verification

Concept

The Design Under Verification (DUV) is the hardware implementation whose behavior is checked by a verification methodology. It is the central artifact addressed by verification plans, stimuli generators, formal properties, SystemVerilog Assertions, and exercisers across pre-silicon and post-silicon platforms. For processor designs, the DUV is typically an RTL pipeline whose behavior is checked against an architectural-state specification using mapping functions and consistency assertions. Stimuli generation for the DUV must address several open design choices (number of generators, abstraction level, online vs. offline generation, dynamic vs. static generation, test length) in order to realize the goals of the verification plan. The DUV is also the target of coverage-guided fuzzing testbenches that cross-check a behavioral reference model against the RTL implementation.

First seen 5/29/2026

Last seen 9/7/2026

Evidence 21 chunks

Wiki v6

WIKI

Definition

A Design Under Verification (DUV) is the hardware design whose behavior is being checked by a verification methodology. The verification plan enumerates a large set of features in the DUV that need to be verified, where each feature is associated with coverage events the verification team expects to observe during the verification process and the methods used to verify the feature. [DUV-definition] [DUV-feature-coverage]

Role in Coverage-Driven Verification

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NEIGHBORHOOD

2 nodes · 1 edges

graph · Design Under Verification · depth=1

RELATIONSHIPS

10 connections

Consistency Assertions ← uses 80% 2e

Consistency assertions provide feedback on the DUV and help ensure correct verification.

Dynamic Test Generation ← uses 100% 2e

Dynamic test generation is fully aware of the state of the DUV and generates based on this information.

Automatic Property Generation ← uses 85% 2e

The approach generates properties that are checked against the design under verification.

Online Test Generation ← uses 100% 1e

Online generation uses information about the state of the environment and DUV for improving generation quality.

Verification Plan mentions → 90% 1e

The verification plan targets features in the Design Under Verification.

Coverage-guided Fuzzing ← uses 95% 1e

Coverage-Guided Fuzzing simulates the RTL Design Under Verification within a fuzzing testbench.

Architectural State uses → 100% 1e

The state of the DUV is described using the architectural state abstraction.

On Parallel Scalable Uniform SAT Witness Generation ← uses 100% 1e

The paper addresses validation of designs under verification.

execution engine ← evaluates 97% 1e

The execution engine runs the generated test case on the design-under-verification.

processor ← part of 88% 1e

A computer processor is given as an example of what the design-under-verification could be.

LINKED ENTITIES

1 links

Coverage-guided Fuzzing USES Extracted graph relationship

CITATIONS

11 sources

11 citations — click to expand

[1] The DUV's behavior is checked by a verification methodology through verification plans, stimuli generators, formal properties, SystemVerilog Assertions, and exercisers across pre-silicon and post-silicon platforms. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[2] Coverage-Driven Verification combines a verification plan of DUV features with random stimuli generators directed by test-templates and coverage analysis tools that feed back on test-template quality. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[3] Stimuli generation for a DUV must address open design choices including number of generators, abstraction level, online vs. offline generation, dynamic vs. static generation, and test length. Stimuli Generation

[4] For a processor DUV, generators and drivers are placed around the design, organized as distributed, single unified, or synchronized generators to balance reuse and coordinated corner-case stimulation. Stimuli Generation

[5] A typical processor verification plan checks all pairs of instructions execute correctly together and that all forwarding mechanisms between pipeline stages work properly. Stimuli Generation

[6] Pre- and post-silicon verification share a common DUV focus but differ in execution speed and observability; limited silicon observability requires using acceleration platforms to measure coverage and build a regression suite of exerciser test-templates. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[7] Threadmill enables a unified pre-/post-silicon methodology by guiding an exerciser through test-templates, using a builder to compile the template and architectural model into an executable exerciser image that runs in an endless loop on the DUV. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[8] In a cross-level CGF testbench for hardware peripherals, the RTL DUV is simulated alongside a TLM reference through a TLM-RTL transactor, with the fuzzer generating inputs that are mapped to interrupt, priority, and threshold configurations; behavioral mismatches stop the fuzzer and expose input patterns for debugging. Cross-Level Verification of Hardware Peripherals

[9] Coverage metrics (line, function, branch) are reported for both the TLM reference and the RTL DUV in absolute and relative numbers and can be used to choose between fast and accurate co-simulations. Cross-Level Verification of Hardware Peripherals

[10] For application-driven co-simulation, the RTL DUV together with the transactor is integrated as a drop-in replacement in a full system Virtual Prototype, enabling co-simulation with the TLM reference and execution of embedded software and operating systems against the DUV. Cross-Level Verification of Hardware Peripherals

[11] Recent tool-augmented LLM approaches generate SystemVerilog Assertions from natural-language specifications by gathering DUV context (e.g., AST-indexed semantic search, JasperGold structural queries) and refining assertions using formal proof feedback over multiple verification rounds. From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation