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21,008 charsRad-hard Microcontroller with Open Access ISA for Space Applications H2020 Programme Space Theme Absint
Milos Krstic, Felipe Kuentzer, Klaus Tittlebach, Cristiano Calligaro, Umberto Gatti, ThalesAlerfia Juan Cueto, Fatima García Donday, Michael Schmidt, Bernhard Schommer, Christian Ferdinand, Axel von Blomberg SYSGO EMBEDDING INNOVATIONS
June 3rd, 2022 9th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications -
Agenda M RAL =
Background
MORAL Project Introduction
MORAL Microcontroller
PEAKTOP Architecture
Specification
Digital Design
Technology and PDK
Memory and Analog IPs
Evaluation Board
MORAL Software
PEAKTOP Toolchain
Compiler and RTSK
Development Status
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MORAL
Background =
Small satellites – 2030 and beyond Low-cost small satellites (from 10 kg to 500 kg) Potential for scientific research and practical applications
Small satellite modern applications Satellite swarms or constellations replacing large satellites Augmented satellite based navigation systems Satellites in commercial aviation Commercial satellite imagery based services Robotic servicing technologies for space applications
5
Mainly powered by traditional electronics Ne Increased capabilities, but reduced reliability ER 57,000 satellites planned through 2029
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Introduction =
MORAL Project – H2020 Space Theme Programme Duration from 01. January 2020 to 30. April 2023 (40 months) Funded by the EC - GA No. 870365 Two main objectives Develop a completely European, ITAR-free microcontroller for space applications Exploitation plan for entering the market 5 partners
Microcontroller
design and test
Specification and po] Evaluation (RTOS development & Compiler) Exploitation
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Introduction =
MORAL in a nutshell Microcontroller based on the novel PEAKTOP architecture, including a novel Instruction Set Architecture (ISA)
Formally-verified C compiler, RTOS, and toolchain
Demonstrator board
Irradiation tests
Aggressive exploitation plan for bringing the product into market
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MORAL Microcontroller - PEAKTOP M RAL =
Why a new processor core architecture? IHP’s PEAKTOP architecture Freely available Complete control over each aspect of the microcontroller ITAR-free Scalable (e.g., to 64-bit) More than TMR and ECC features
PEAKTOP provides mixed criticality support Multiple functions with different criticalities and assurance levels to co-exist in the microcontroller architecture General Purpose Register (GPR) banks can be dynamically grouped Dual-, Triple- or Quadruple-Modular Redundant (DMR/TMR/QMR) module to increase the fault tolerance
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PEAKTOP Architecture M RAL =
IHP’s own processor Open ISA PEAKTOP Bootrom execution pipeline Core architecture characteristics SRAM RISC architecture System Up to 64 GPR IEEE 754 compliant Floating Point Unit (FPU) endl [bd Optional Digital Signal Processing (DSP) extension New ISA is fully orthogonal, regular, and circular Multiprocessing support (cache coherence, synchronization support, atomic transfers) Configurable addressing space: up to 64-bit; virtual address space is up to 128-bits 32-bit wide instructions up to 3 operands 2-level Memory Protection Unit (MPU), or (optionally) 2-level Memory Management Unit (MMU) Optional L1 (separate data/instruction) cache, and L2 cache
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M
MORAL Microcontroller – Specification
PROM
Memory FLASH
PEAKTOP CORE controller SRAM
PEAKTOP CHAM Ss SDRAM
execution pipeline ADC, DAC with FPU and DSP x
7 § || cess,
Interrupt Debug User 2 ==
controller unit timer 12C, SpaceWire
Microcontroller ny K
Na
System-on-Chip brid ali
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MORAL Microcontroller – Specification M RAL =
256/512 Kbyte SRAM Error Detection and Correction (EDAC) protection unit
PROM
1 x Interrupt Controller PEAKTOP CORE Memory controller SRAM 32 interrupt lines PEAKTOP 5 SDRAM execution pipeline =a 6 x Timers Interrupt Debug User H PEE 2x system + 4x user timers controller] fini] 5 Microcontroller reer | 64 x GPIO ports “Watchdog. | Shared with internal peripherals I/Os
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MORAL Microcontroller – Specification M RAL =
Peripherals PROM, FLASH, SRAM, SDRAM 1 x 8-channel 12-bit ADC 2 x 12-bit DAC 2 x CAN 2.0 modules | Controller Timer Timer +EDAC +EDAC 4 x UART interfaces EE 2 x SPI interfaces APEPeripheral Bus 2 x SpaceWire interfaces (incl. RMAP protocol) 1 x MIL-STD 1553C bus interface (incl. redundant bus) 2 x I2C interfaces 1 x 8-channel PWM generator 4 x Pulse counters 1 x Watchdog timer
Rad-Hard Specification Total ionizing dose (TID) 100 krad (Si) Single event upset (SEU) for the processor’s digital core >30 MeVcm²/mg Single event latch-up (SEL) >60 MeVcm²/mg L AMICSA‘22 Workshop June 3, 2022 10
MORAL Microcontroller – Digital Design M RAL = Processor core design |r =| PEAKTOP previously developed, implemented, and = H H | General H Special tested in IHP 130nm technology H FPU design and redesigned of MPU to support the RTSK needs ALUPUoe JI TR via wl] Erp Peripherals design an integration |) reer]| | | = == MIL-STD 1553C designed at IHP : REE Peripheral in the specification integrated | hw Data transfer| i Control valid (SUM Copy): Verification Moral testbench Carried every step of the design, from RTL simulations RAM || ROM to post-synthesis, and in FPGA
Clock
Reset —
L AMICSA‘22 Workshop MIL1553 ... CAN June 3, 2022 11
MORAL Microcontroller – Technology and PDK
Commercially available IHP Technologies – Multi Project Wafer (MPW)
Baseline CMOS technologies
Dual-gate 0.13um CMOS
SGB25V SG25H3 $G13G2
npn-HBTs up to npn-HBTs up to npn-HBTs up to npn-HBTs up to f/f L7V | | £ ,, 1.65V Voce Up to 7V Upto 7V Vey | | =120/330GHz 2.5V SGB25RH variant Qualified
SG25H5-EPIC Stable/ ( 3 G135Cu || SG13G2Cu Early access LBE, TS | $6135 135 with || SG135 with Ge-PD, MZM, WG, GC... variant ||
Backside RDL
with Under W2W bonding Next generation SG13G3 Cu-BEOL development RadHard MOS devices L AMICSA‘22 Workshop June 3, 2022 12
MORAL Microcontroller – Technology and PDK M < >RAL =
IHP SG13S/RH - PDK for Space Applications
SG13S/RH
Process Description SiGe HBTs npn Peak fT /fMAX 220/340GHz
130nm Dual Gate –Oxide CMOS
(VDD=+1.2V, +3.3V ; TOX = 2nm / 7nm)
Commercial Qualification completed 2014
Based on JEDEC Standard JP001.01
EPPL/QML/QPL (ESCC QPL, ESCC QML, MIL QPL, JAXA QPL) Evaluation ongoing
PDK Av ailability In dev elopment -Early Access
Access Status NDA/EXPORT License
CMOS Std Cell Core and IO Libraries IHP IXC013RH (~ 90 cells)
Radiation Assessment (Digital) 100krad(Si) – 300krad(Si)
TID SEU/SEL completed
CMOS Libraries
SEL Threshold > 65MeV/cm²/mg
(RHBD IHP cells)
SEU Threshold > 30MeV/cm²/mg
(IHP RTMR FF)
Ev aluation Testing Activ ity started
in acc. ESCC No. 2269010
Operation Temperature (max rated TJ) -55°C to +125°C (TBC)
Test Vehicles TCV,
in acc. ESCC No. 2269010 DEC –I DEC-II(CMOS, Bipolar)
RIC in progress
Radiation Tests completed
TCV (Devices, analog) „
DECs (Digital, Analog BiCMOS) DEC-I (SEU/SEL), Early structures
RIC (Mixed-Signal IC) planned
— | Endurance Testing HT & RT Activ ity started HBT npn- devices (qualification of technology for general purpose applications done) HBT lifetime determination CMOS devices CMOS Core & IO Std Cell Library
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MORAL Microcontroller – Memory and Analog IPs M RAL =
Rad-hard SRAMs Input Buffer Input Buffer Input Buffer Input Buffer
Independent decoding schemes Row DEMUX Row DEMUX Row DEMUX Row DEMUX
Column Column Column Column
DEMUX DEMUX DEMUX DEMUX
6T SRAM cell Read/Write Read/Write Read/Write Read/Write
Column Driver Column Driver Column Driver Column Driver
Island Guard Ring (IGR) instead of Enhanced Guard Ring (EGR)
Tradeoff between inter-device leakage degradation and area Equalizer | Equalizer | Equalizer | Equalizer
DIN<0> DOUT<0> DIN<1> DOUT<1> DIN<2> DOUT<2> DIN<7> DOUT<7>
64kbit
32kbit
L AMICSA‘22 Workshop Single bit macro Test Chip 1 June 3, 2022 14
Row Driver Bus
Matrix Bus Row Driver Bus
Matrix Bus Row Driver Bus
Matrix Bus
Row Driver Bus
Matrix Bus
MORAL Microcontroller – Memory and Analog IPs M RAL =
Rad-hard 12-bit DAC Architecture based on resistor divider (Kelvin divider)
= he Test Chips 2 and 4
JL = 73
Rad-hard 12-bit ADC Architecture - SAR (Successive Approximation Register) Single-ended and differential ls 3 3
Test Chips 3 AMICSA‘22 Workshop June 3, 2022 15
MORAL Microcontroller – FPGA Board
Implementation on programmable hardware platform Early hardware debug Early tests of complex software Ex.: Operating system, compiler and assembler tool-chain, and simple applications
Project dissemination Opportunity for the academia to know and experiment with the new architecture
For availability of an evaluation board use
! the contact form in
_ www.moral-project.com = R MORAL’s website.
a L AMICSA‘22 Workshop FPGA board June 3, 2022 16
MORAL Software – PEAKTOP Toolchain M RAL =
Open source toolchain Multiprocessor Debugger Instruction Set Simulator Complete ISA and tools documentation
= [EH = Ee
|L AMICSA‘22 Workshop https://www.moral-project.eu/acad_open_source.html June 3, 2022 17
MORAL Software – Compiler and RTSK M RAL =
CompCert – 2021 ACM Software System Award Compiler for C programming language
The only formally verified compiler in the market Free for evaluation, research, and education Commercial licenses distributed by AbsInt
Porting of CompCert for the PEAKTOP architecture Implementation of binary utilities Bu | Optimization and formal verification les |= — Semi-automatic testing with FPGA board
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MORAL Software – Compiler and RTSK M RAL =
Real Time Separation Kernel - RTSK Provides isolated partitions Partition Partition Communication between partitions Partition is an execution environment that Serves as a virtual CPU Separation Kernel Contains a guest operating system CPU RTSK tailored for the PEAKTOP microcontroller Microcontroller for space platforms provide limited RAM for any COTS Must have a very low footprint
Separation kernel prototype First release for project partners Running on the FPGA board
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Development Status =
MORAL Project | Status | Period | Comments |
Prototype specification done Q2 2020 Completed
Prototype design done Q1 2021 FPU, DSP support, and M1553
Prototype functional tests done Q1 2021 Integration and functional simulations
Prototype emulation done Q2 2021 Running on the FPGA board
Memory and analog IPs design done Q4 2021 SRAM, DAC, and ADC
Test chips fabrication done Q4 2021 Four test chips
RTSK done Q4 2021 Running on the FPGA board
Compiler - CompCert done Q1 2022 Porting and verification completed
SRAM, DAC, and ADC test chips evaluation done Q2 2022 12-bit DAC and 12-bit ADC
Drivers, library, and software tools Q1 2023 Specification on-going
Prototype fabrication and testing Q2 2022 Layout on-going
Prototype stress tests Q1 2023 Radiation test PCB on-going
Prototype demonstrator Q1 2023 Demonstrator PCD on-going
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MORAL Website M<RAL =
Access for more information and news about MORAL Links for the project Social Media PEAKTOP toolchain download
Export-free Rad-hard Microcontroller for Space Applications
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