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2026-09-21

5 items 92 entities 108 connections

2. Overview — RISC-V CSRBox Generator 1.0.2 documentation

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Processed 18 entities and 19 relations.

CSRBox riscv-config Bluespec SystemVerilog Bluesim Verilog RISC-V RISC-V U CSR ISA Spec YAML Grouping Spec YAML Attribute YAML CSR Decoder CSR Defines RISC-V WARL CSR Daisy-Chain Flow Machine CSRs Supervisor CSRs User CSRs

Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees

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Processed 8 entities and 12 relations.

ARM Register renaming for temporaries Stack slot permutation for locals Instruction combining Stack frame offset variation Memory allocation size variation Equivalent instruction sequences Constant loading via literal pool

Transmeta Crusoe Hardware, Software, and Development

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Processed 12 entities and 10 relations.

Automated test farm Automatic instruction-level test generators Automatic system-level test generators Biased random test generation VLIW test suites x86 test suites Industry-standard test suites Acceptance test suites Application and OS-based tests Corner-case tests Performance tests Benchmarks used as tests

FLAME: Enhancing Functional Coverage in

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Processed 31 entities and 35 relations.

FLAME Constrained Random Verification (CRV) Coverage-Guided Fuzzing (CGF) RISCV-DV Cascade LLM-PVISA LLM-PVFunc ChatFuzz VerilogReader LLM4DV MorFuzz DifuzzRTL Retrieval-Augmented Generation (RAG) Chain-of-Thought (CoT) Zero-shot prompting Few-shot learning Documents–Instructions–Programs CoT Instruction Set Simulator (ISS) RISC-V GCC Synopsys VCS C test programs RISC-V instruction sequences GPT-3.5-Turbo CodeLlama-7B-Instruct CodeLlama-13B-Instruct Phind-CodeLlama-34B-v2 ChatGPT Llama 3 RISC-V Directed testing Random testing

ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

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Processed 23 entities and 32 relations.

ConfigDrivenV Python UVM SystemVerilog Constrained random test generation Directed testing Python-UVM co-verification Golden reference model Random instruction generation File I/O bridge (Python to UVM) $fscanf instr.hex checkpoints.mem golden.mem UVM sequence cpu_test.sv RISC-V Power ISA SystemVerilog constraint randomization UVM Verification of RISC-V Instruction Set (ICAECA 2024) A UVM based Reusable Framework for End-To-End Verification of Power ISA Cores (IJISAE 2024) Directed Test Generation for Hardware Validation: A Survey (ACM CS 2023) Automated Testing, Verification and Repair of RTL Hardware Designs (UCB EECS TR 2024-157)