ARM Instruction Set Architecture
ISAARM is a reduced instruction set computer (RISC) instruction set architecture widely used in embedded, mobile, edge, and server-class systems. It supports advanced emulation, virtualization, and heterogeneous compute, and exhibits well-known code-level variations that complicate cross-translation and obfuscation tasks.
First seen 9/21/2026
Last seen 9/28/2026
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Overview
ARM is a load/store RISC instruction set architecture that originated in the Acorn RISC Machine project and has become one of the dominant ISAs for embedded, mobile, and edge computing devices. The architecture emphasizes a large uniform register file, fixed-length instructions (in AArch32/A64 encodings), and simple addressing modes, which together enable efficient pipelined implementations. ARM designs are now deployed across a broad range of system-on-chip (SoC) devices, from microcontrollers to application processors that pair ARM CPU cores with GPUs in heterogeneous multi-processor SoCs (HMPSoCs).
Architectural characteristics
NEIGHBORHOOD
4 nodes · 7 edgesgraph · ARM · depth=1
RELATIONSHIPS
10 connectionsThe register-renaming example uses ARM registers and instructions, indicating the technique targets the ARM ISA.
Stack slot permutation is demonstrated with ARM stack/frame-pointer addressing, indicating ARM as the target ISA.
Instruction combining is illustrated using ARM instructions and addressing.
Variation of stack frame offsets is shown with ARM byte store and frame-pointer offsets.
Allocation size change example uses ARM immediate move into r0.
Equivalent sequences are exemplified with ARM conditional and arithmetic instructions.
Literal-pool constant loading is an ARM-specific idiom, indicating the technique targets ARM.
ARM is listed among the evaluated ISAs.
ARM is one of the ISAs over which Icicle's fidelity is demonstrated.
The abstract characterizes Fuzzware specifically as an ARM firmware fuzzer.
LINKED ENTITIES
7 linksRegister renaming for temporaries TARGETS_ISA Extracted graph relationship
Stack slot permutation for locals TARGETS_ISA Extracted graph relationship
Instruction combining TARGETS_ISA Extracted graph relationship
Stack frame offset variation TARGETS_ISA Extracted graph relationship
Memory allocation size variation TARGETS_ISA Extracted graph relationship
Equivalent instruction sequences TARGETS_ISA Extracted graph relationship
Constant loading via literal pool TARGETS_ISA Extracted graph relationship
CITATIONS
9 sources9 citations — click to expand
[1] Different general-purpose registers can be chosen for temporary ARM values while preserving data flow (e.g., mov r2 vs. mov r3). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[2] Local ARM variables can be permuted across stack slots (e.g., swapping [fp, #-8] and [fp, #-12]) while preserving access patterns. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[3] Multiple ARM instructions can be combined into a single equivalent instruction, such as merging a mov and a str into a single str using the source register. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[4] ARM stack-frame offsets can vary across compilations while still providing correct variable access (e.g., [fp, #-21] vs. [fp, #-17]). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[5] ARM memory allocation sizes can vary if still sufficient for program needs (e.g., mov r0, #400 vs. mov r0, #800). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[6] Different ARM instruction sequences can produce the same logical result, such as computing an absolute value via cmp/and/rsblt versus rsbs/and/rsbpl. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[7] Large ARM constants can be loaded either via a single mvn immediate or via a PC-relative ldr from a .word literal pool entry. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[8] ARM-on-ARM virtualization using Linux KVM inside SystemC-TLM virtual platforms achieves up to 10× speedup over ISS-based models, and more than 100× on some benchmarks. High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms
[9] Extended ARM Compute Library with native transformer kernels achieves up to 3× faster transformer inference on ARM-based embedded boards, and cooperative CPU-GPU execution on ARM HMPSoCs reduces latency by an additional up to 15.72%. Fast Transformer Inference on ARM-Based HMPSoCs