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ARM Instruction Set Architecture

ISA WIKI v1 · 9/21/2026

ARM is a reduced instruction set computer (RISC) instruction set architecture widely used in embedded, mobile, edge, and server-class systems. It supports advanced emulation, virtualization, and heterogeneous compute, and exhibits well-known code-level variations that complicate cross-translation and obfuscation tasks.

Overview

ARM is a load/store RISC instruction set architecture that originated in the Acorn RISC Machine project and has become one of the dominant ISAs for embedded, mobile, and edge computing devices. The architecture emphasizes a large uniform register file, fixed-length instructions (in AArch32/A64 encodings), and simple addressing modes, which together enable efficient pipelined implementations. ARM designs are now deployed across a broad range of system-on-chip (SoC) devices, from microcontrollers to application processors that pair ARM CPU cores with GPUs in heterogeneous multi-processor SoCs (HMPSoCs).

Architectural characteristics

  • Load/store RISC design. Memory accesses are explicit and restricted to load and store instructions; arithmetic and logical operations operate only on registers.
  • Large uniform register file. General-purpose registers (r0–r12 in AArch32, plus link registers, stack pointer, and program counter) provide a flat register space that simplifies compiler register allocation.
  • Literal pools. The architecture supports loading 32-bit (or larger) constants either via immediate operands or, when the value cannot be encoded in a single instruction, from a nearby literal pool addressed by a PC-relative ldr (chunk dd53ba47-a1d7-483b-97a0-3616bb939c8c).
  • Stack frame conventions. Compilers emit standard prologue/epilogue sequences with frame pointer–relative accesses to local variables (chunk dd53ba47-a1d7-483b-97a0-3616bb939c8c).

Code-level variation on ARM

Because ARM is a compiler-friendly RISC target with flexible encoding choices, equivalent ARM programs can be expressed in many syntactically different but semantically identical ways. These variations are documented in transpilation studies between complex instruction set computing (CISC) source ISCs and RISC targets such as ARM:

  • Register renaming for temporaries. Different general-purpose registers can be chosen for temporary values while data flow is preserved (e.g., mov r2, r0 vs. mov r3, r0) [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Stack slot permutation for locals. Local variables may be stored at different stack offsets while preserving correct access patterns (e.g., swapping [fp, #-8] and [fp, #-12]) [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Instruction combining. Multiple instructions can be collapsed into a single equivalent instruction (e.g., mov r3, r0; str r3, [fp, #-8] vs. str r0, [fp, #-8]) [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Stack frame offset variation. Stack-frame offsets for individual locals can differ between compilations while remaining functionally correct (e.g., [fp, #-21] vs. [fp, #-17]) [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Memory allocation size variation. Allocation sizes for buffers can vary across compilations if still sufficient for program needs (e.g., mov r0, #400 vs. mov r0, #800) [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Equivalent instruction sequences. Distinct sequences can compute the same logical result, such as an absolute-value computation written with cmp/and/rsblt versus rsbs/and/rsbpl [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Constant loading via literal pool. Large constants may be loaded either via a single mvn immediate or via a PC-relative ldr from a nearby .word literal pool entry (e.g., mvn r3, #-2147483648 vs. ldr r3, .L8; .L8: .word 2147483647) [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].
  • Compiler symbol naming. Compiler-generated symbol suffixes (e.g., .word out.4781 vs. .word out.4280) can differ while still referring to the same underlying data object [Evidence: dd53ba47-a1d7-483b-97a0-3616bb939c8c].

These source-level variations complicate naive diff-based equivalence checks and motivate testing-guaranteed approaches for CISC-to-RISC transpilation.

ARM in virtualization and emulation

ARM's hardware virtualization extensions enable high-fidelity, high-performance emulation of ARM-based systems on ARM hosts. Recent work demonstrates ARM-on-ARM virtualization inside SystemC-TLM virtual platforms by leveraging the Linux KVM hypervisor to run target software natively on ARM-based hosts. This approach eliminates the need for a traditional instruction-set simulator for the target and achieves up to a 10× speedup over ISS-based virtual platform models on compute-intensive workloads, with more than 100× speedups on some benchmarks [Evidence: arxiv:2505.12987v2].

ARM in edge AI and heterogeneous compute

The ARM Compute Library (ARM-CL) provides optimized inference kernels for ARM-based edge devices, originally focused on convolutional neural networks. Recent extensions add native transformer kernels to ARM-CL, achieving up to three times faster transformer inference than state-of-the-art CPU/GPU baselines on ARM-based embedded boards. On heterogeneous multi-processor SoCs that combine ARM CPUs with on-chip GPUs, cooperative CPU-GPU transformer execution—memory-intensive operations on the CPU and highly parallelizable compute on the GPU—reduces inference latency by an additional up to 15.72% over the best single-processor ARM-CL configuration [Evidence: arxiv:2606.02836v1].

Cross-references

See also the following code-transformation techniques that target the ARM ISA:

  • Register renaming for temporaries
  • Stack slot permutation for locals
  • Instruction combining
  • Stack frame offset variation
  • Memory allocation size variation
  • Equivalent instruction sequences
  • Constant loading via literal pool

LINKED ENTITIES

7 links
Register renaming for temporaries TARGETS_ISA
Stack slot permutation for locals TARGETS_ISA
Instruction combining TARGETS_ISA
Stack frame offset variation TARGETS_ISA
Memory allocation size variation TARGETS_ISA
Equivalent instruction sequences TARGETS_ISA
Constant loading via literal pool TARGETS_ISA

CITATIONS

9 sources
9 citations
[1] Different general-purpose registers can be chosen for temporary ARM values while preserving data flow (e.g., mov r2 vs. mov r3). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[2] Local ARM variables can be permuted across stack slots (e.g., swapping [fp, #-8] and [fp, #-12]) while preserving access patterns. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[3] Multiple ARM instructions can be combined into a single equivalent instruction, such as merging a mov and a str into a single str using the source register. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[4] ARM stack-frame offsets can vary across compilations while still providing correct variable access (e.g., [fp, #-21] vs. [fp, #-17]). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[5] ARM memory allocation sizes can vary if still sufficient for program needs (e.g., mov r0, #400 vs. mov r0, #800). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[6] Different ARM instruction sequences can produce the same logical result, such as computing an absolute value via cmp/and/rsblt versus rsbs/and/rsbpl. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[7] Large ARM constants can be loaded either via a single mvn immediate or via a PC-relative ldr from a .word literal pool entry. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
[8] ARM-on-ARM virtualization using Linux KVM inside SystemC-TLM virtual platforms achieves up to 10× speedup over ISS-based models, and more than 100× on some benchmarks. High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms
[9] Extended ARM Compute Library with native transformer kernels achieves up to 3× faster transformer inference on ARM-based embedded boards, and cooperative CPU-GPU execution on ARM HMPSoCs reduces latency by an additional up to 15.72%. Fast Transformer Inference on ARM-Based HMPSoCs