Instruction combining

Technique

Instruction combining is a program-synthesis and code-transformation technique that replaces a sequence of multiple instructions with a single equivalent instruction (or a shorter equivalent sequence) while preserving the program's observable behavior. It is used in chip verification, ISA transpilation, and other correctness-oriented contexts where two syntactically different instruction streams must be shown to compute the same result.

First seen 9/21/2026

Last seen 9/21/2026

Evidence 1 chunks

Wiki v1

WIKI

Instruction combining

Definition

Instruction combining refers to the process of collapsing two or more consecutive instructions into a single instruction (or, more generally, a shorter sequence) that has the same semantic effect on program state. It is the inverse transformation of instruction decomposition and is closely related to the broader notion of equivalent instruction sequences.

In practical terms, an instruction combiner recognizes a pattern such as

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

ARM targets ISA → 78% 1e

Instruction combining is illustrated using ARM instructions and addressing.

Equivalent instruction sequences part of → 82% 1e

Combining multiple instructions into a single one is a form of producing an equivalent instruction sequence.

LINKED ENTITIES

2 links

ARM TARGETS_ISA Extracted graph relationship

Equivalent instruction sequences PART_OF Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] SEPE-SQED uses program synthesis to find instruction combinations semantically equivalent to original instructions, enabling detection of single-instruction bugs and producing shorter equivalent traces. SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution

[2] Instruction combining in CISC-to-RISC transpilation replaces a multi-instruction sequence with a single equivalent instruction (e.g., fusing a register move with a subsequent store into a direct store). Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees

[3] Equivalent multi-instruction sequences that compute the same logical result (e.g., alternative encodings of a sign-and-magnitude operation) are also considered instruction-combining transformations in transpilation edit-distance analysis. Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees