Golden reference model

Technique

A golden reference model is a trusted software or specification-level model used to compute expected behavior for a hardware design under test. In RTL verification flows it can generate expected register states, memory/checkpoint files, or final outputs that a UVM scoreboard compares against DUT results; in hardware fuzzing it also serves as an oracle for detecting divergences.

First seen 9/21/2026

Last seen 9/21/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

A golden reference model is a trusted behavioral model used as the expected-result oracle for a design under test. In the supplied RTL-verification evidence, the model is implemented as a software register-file model: each generated instruction is applied to the software state, and the resulting PC R0 R1 R2 R3 snapshot is written as the ground truth against which hardware outputs are compared. [C1]

Golden reference models are commonly paired with automated stimulus and self-checking infrastructure. In a UVM-style flow, the reference model produces expected values, the DUT produces actual values, and a scoreboard reports pass/fail mismatches. [C2]

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NEIGHBORHOOD

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RELATIONSHIPS

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ConfigDrivenV ← uses 93% 1e

The Python layer acts as a software reference model to predict expected outcomes.

random instruction generation ← part of 84% 1e

The golden model produces random instruction sequences as part of its operation.

A UVM based Reusable Framework for End-To-End Verification of Power ISA Cores (IJISAE 2024) ← uses 80% 1e

A software predictor provides expected register states compared by the scoreboard.

Automated Testing, Verification and Repair of RTL Hardware Designs (UCB EECS TR 2024-157) ← evaluates 88% 1e

It highlights the effectiveness of comparison against a golden model.

Python-UVM co-verification part of → 85% 1e

The two-layer architecture pairs a Python golden model with a UVM testbench.

LINKED ENTITIES

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A UVM based Reusable Framework for End-To-End Verification of Power ISA Cores (IJISAE 2024) USES Extracted graph relationship

Automated Testing, Verification and Repair of RTL Hardware Designs (UCB EECS TR 2024-157) EVALUATES Extracted graph relationship

ConfigDrivenV USES Extracted graph relationship

random instruction generation PART_OF Extracted graph relationship

Python-UVM co-verification PART_OF Extracted graph relationship

TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities USES The public arXiv context explicitly names TheHuzz as using golden-reference models for processor instruction fuzzing.

CITATIONS

10 sources

10 citations — click to expand

[1] C1: In the cited RTL flow, the golden reference model acts as ground truth by applying each generated instruction to a software register-file model and writing PC/register checkpoints. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[2] C2: A UVM sequence can read golden-reference files with $fscanf, drive the DUT, capture actual values, and compare expected and actual values in a scoreboard. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[3] C3: ConfigDrivenV generates random CPU instructions by selecting opcodes, random destination registers, and signed 8-bit immediates. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[4] C4: ConfigDrivenV exports instr.hex, checkpoints.mem, and golden.mem in hexadecimal text formats readable by SystemVerilog $fscanf. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[5] C5: The ConfigDrivenV Python model masks arithmetic results with 0xFFFF to match 16-bit modular overflow behavior. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[6] C6: The ConfigDrivenV scoreboard compares Python-predicted and DUT actual register values using SystemVerilog === to handle 4-value logic and logs mismatches. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[7] C7: ConfigDrivenV is described as a two-layer Python-UVM co-verification framework with Python golden-reference integration, validation on a 16-bit RISC processor and UART controller, and bug-injection experiments. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[8] C8: In the ConfigDrivenV CPU experiment, correct RTL passed 100 random instructions, while a corrupted ADD/SUB RTL variant produced scoreboard failures with expected-versus-actual logs. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

[9] C9: TheHuzz is an instruction fuzzer for processors using golden-reference models; it generates assembly-level instructions and reports finding hardware bugs exploitable from software. TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities

[10] C10: A hardware-fuzzing survey identifies reliable and scalable golden reference models as an unmet need across ISA, microarchitecture, and RTL fuzzing layers. SoK: ARCUS: On the Efficiency and Efficacy of Hardware Fuzzing