ConfigDrivenV

Tool

First seen 8/6/2026

Last seen 9/21/2026

Evidence 14 chunks

NEIGHBORHOOD

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RELATIONSHIPS

31 connections

SystemVerilog uses → 100% 3e

The testbench layer is written in SystemVerilog.

Python uses → 100% 3e

The framework integrates a Python layer for stimulus generation and reference modeling.

constrained-random test generation uses → 100% 3e

Stimulus is generated using a constrained-random approach on the Python side.

Self-Checking Scoreboard uses → 100% 2e

ConfigDrivenV performs cycle-accurate comparison via a self-checking scoreboard.

Universal Verification Methodology (UVM) uses → 100% 2e

ConfigDrivenV's UVM layer is implemented in SystemVerilog following UVM methodology.

ModelSim Intel FPGA Starter Edition uses → 100% 2e

ConfigDrivenV uses ModelSim Intel FPGA Starter Edition for simulation.

ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard ← introduces 100% 2e

The paper introduces ConfigDrivenV as a novel Python-UVM co-verification framework.

File I/O Bridge (Python to UVM via $fscanf) uses → 100% 2e

ConfigDrivenV bridges Python and UVM layers via file I/O using $fscanf.

16-bit RISC Processor evaluates → 100% 2e

ConfigDrivenV is validated on a custom 16-bit RISC-style processor.

UART Controller evaluates → 100% 2e

ConfigDrivenV is validated on a UART serial communication controller.

Bug Injection uses → 100% 2e

ConfigDrivenV employs bug injection experiments to validate testbench sensitivity.

Python-UVM Co-Verification implements → 100% 2e

ConfigDrivenV implements a Python-UVM co-verification approach.

Two-Layer Verification Architecture implements → 100% 2e

ConfigDrivenV is built on a two-layer pipeline architecture.

cycle-accurate simulation uses → 100% 2e

ConfigDrivenV performs cycle-accurate comparison in its scoreboard.

Random Instruction Sequence Generation uses → 100% 2e

ConfigDrivenV's Python layer generates random instruction sequences.

TLM Analysis Ports uses → 95% 2e

ConfigDrivenV's UVM environment connects components via TLM analysis ports.

simple_cpu.v evaluates → 100% 2e

ConfigDrivenV evaluates simple_cpu.v as DUT1.

uart_tx.v evaluates → 100% 2e

ConfigDrivenV evaluates the UART TX component.

simple_cpu_buggy.v evaluates → 100% 2e

ConfigDrivenV evaluates simple_cpu_buggy.v and detects all introduced bugs.

uart_rx.v evaluates → 100% 2e

ConfigDrivenV evaluates the UART RX component.

Golden Reference Model uses → 100% 2e

ConfigDrivenV uses a Python golden reference model for expected state computation.

cpu_test.sv ← part of 75% 1e

The framework’s UVM testbench includes the cpu_test.sv test class/module.

RTL verification implements → 100% 1e

ConfigDrivenV implements automated RTL verification.

Functional Verification implements → 100% 1e

ConfigDrivenV implements functional verification for digital hardware designs.

formal verification ← compares with 85% 1e

ConfigDrivenV targets the simulation domain as an alternative to formal verification.

RISC-V Instruction Set Verification mentions → 80% 1e

ConfigDrivenV's paper surveys RISC-V instruction set verification as related work.

UVM uses → 95% 1e

Its verification environment is a UVM testbench.

Golden reference model uses → 93% 1e

The Python layer acts as a software reference model to predict expected outcomes.

random instruction generation uses → 86% 1e

The stimulus space is explored via randomly generated instructions.

Python-UVM co-verification implements → 92% 1e

It realizes a co-verification flow coupling Python and a UVM testbench.

File I/O bridge (Python to UVM) uses → 86% 1e

Integration is achieved through files read/written across layers.