16-bit RISC Processor

Concept

The 16-bit RISC Processor is a custom single-cycle RTL design under test (DUT 1) in the ConfigDrivenV framework, implemented in SystemVerilog as simple_cpu.v. It features a 4×16-bit register file, an 8-bit program counter, and a single-cycle execution FSM. The processor supports five opcodes (NOP, ADD, SUB, MOV, XOR, HALT) encoded in a 16-bit instruction format, and is verified by ConfigDrivenV with 100% pass rate on correct RTL and 100% bug detection on corrupted RTL.

First seen 8/6/2026

Last seen 8/6/2026

Evidence 6 chunks

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16-bit RISC Processor

Overview

The 16-bit RISC Processor is one of two designs under test (DUTs) validated by the ConfigDrivenV Python-Integrated UVM verification framework. It is implemented as a custom RISC-style processor in SystemVerilog (file: simple_cpu.v) and serves as DUT 1 in the ConfigDrivenV testbench pipeline. ConfigDrivenV achieves 100% verification accuracy on the correct RTL (PASS=100, FAIL=0) across all 5 opcodes, all 4 destination registers, and the full signed immediate range, and 100% bug detection effectiveness on deliberately corrupted RTL [b6b66b496-5c1e-4ae0-a78a-2658594b58b2].

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RELATIONSHIPS

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ConfigDrivenV ← evaluates 100% 2e

ConfigDrivenV is validated on a custom 16-bit RISC-style processor.

simple_cpu.v ← implements 100% 2e

simple_cpu.v is the RTL implementation of the 16-bit RISC processor DUT.

LINKED ENTITIES

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ConfigDrivenV EVALUATES Extracted graph relationship

simple_cpu.v IMPLEMENTS Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] The processor features a 4×16-bit register file, an 8-bit program counter, and a single-cycle execution FSM. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[2] The instruction set includes NOP (0x0), ADD (0x1), SUB (0x2), MOV (0x3), XOR (0x4), and HALT (0xF). ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[3] Instruction encoding follows the 16-bit format: bits [15:12] hold the opcode, bits [9:8] hold rd, and bits [7:0] hold the immediate value. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[4] Register state tracking is achieved through a four-element Python list, where each arithmetic operation applies bitwise AND with 0xFFFF to enforce 16-bit width constraints. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[5] The correct RTL passed 100% of instructions spanning all 5 opcodes, all 4 destination registers, and the full signed immediate range (-128 to +127); the buggy RTL achieved 0% pass rate. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[6] The UVM scoreboard uses the SystemVerilog === operator for comparison, which handles 4-value logic (0, 1, X, Z) correctly. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[7] Test depth is controlled by the NUM_INSTR variable, scaling verification from 30 to 1000 instructions without modifying any UVM code. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

[8] The processor is implemented as simple_cpu.v and serves as DUT 1 in the ConfigDrivenV framework. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard