Architectural CPU Vulnerability

Concept

An architectural CPU vulnerability is a security-relevant mismatch between a processor's architectural specification and its actual implementation, as distinguished from transient-execution attacks that exploit microarchitectical optimizations while remaining architecturally correct. Such vulnerabilities can produce direct, reliable exploitation primitives including denial of service, arbitrary memory read/write, privilege escalation, and cryptographic key recovery, and have been demonstrated in commercial RISC-V CPUs (e.g., T-Head XuanTie C906, C908, C910) as well as the historic Pentium F00F bug.

First seen 6/11/2026

Last seen 9/1/2026

Evidence 10 chunks

Wiki v2

WIKI

Definition

An architectural CPU vulnerability is a security-relevant architectural bug: a mismatch between a CPU's specification and its implementation. The RISCVuzz paper contrasts these bugs with transient-execution attacks such as Meltdown and Spectre, which exploit optimizations such as out-of-order and speculative execution but still follow the architectural specification, leaking data only through microarchitectural traces. Architectural bugs, by contrast, can produce direct, reliable exploitation primitives with severe security impact.

Security relevance

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Pentium F00F Bug ← mentions 85% 1e

The Pentium F00F Bug is cited as a historical example of an architectural CPU vulnerability.

CITATIONS

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28 citations — click to expand

[1] An architectural CPU vulnerability is a security-relevant mismatch between a CPU's specification and its implementation, distinct from transient-execution attacks that follow the architectural specification but leak through microarchitectural traces. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[2] The GhostWrite attack on the T-Head XuanTie C910 allows unprivileged users to read and write arbitrary memory, including machine-mode code and MMIO-mapped devices, fully breaking confidentiality and integrity. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[3] Two end-to-end attacks escalate privileges to root and machine mode by using GhostWrite to inject and execute code in supervisor- and machine-mode contexts. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[4] GhostWrite can be used on cryptographic keys to mount an effective fault attack that fully recovers a 2048-bit RSA key within 30 minutes. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[5] The GhostWrite vulnerability can be exploited by unprivileged users in the cloud and was reproduced on Scaleway's TH1520 bare-metal instances. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[6] The C906 and C908 CPU-halting instruction sequences can be triggered by any unprivileged application and also work from inside Docker containers. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[7] The only mitigation identified for vector-extension bugs such as GhostWrite is disabling the extension, which incurs up to 77% overhead in rvv-bench and is not practical for entities relying on the vector extension. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[8] No mitigation exists for the C906 CPU-halting bug because the responsible vendor extension cannot be disabled. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[9] T-Head acknowledged and reproduced GhostWrite and the C906 CPU-halting sequence but had not yet answered about the C908 CPU-halting instructions; Scaleway reproduced GhostWrite and is rolling out kernel patches that disable the vector extension. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[10] RISCVuzz reports a segmentation fault in the latest version of QEMU. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[11] The base instruction set of tested RISC-V CPUs is tested significantly better than complex extensions such as the vector extension, and even open-source cores like the C910 have hardware implementations that differ from the released source. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[12] RISCVuzz categorizes findings into address-handling bugs, decoder bugs, ISA incompatibilities, and fault-reporting issues. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[13] The C906 and C910 execute half-precision floating-point instructions `fsqrt.h` and `fmv.x.h` even when the rs2 field is set to 0, contrary to the ISA specification. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[14] The C906 and C910 do not ignore writes to bits 8 to 10 of the `fcsr` register, contrary to the ISA specification. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[15] The C910 and C908 each support a different subset of vector instructions; some instructions do nothing, others produce unexpected results, and some are not implemented at all. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[16] Cache-block management instructions such as `cbo.inval` crash QEMU 9.0.0 and 8.2.2 with a segmentation fault; truncating vector conversion instructions such as `vfncvt.rtz.x.f.w` crash QEMU 7.2.0 due to an assertion. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[17] SiFive CPUs tend to raise bus faults while T-Head CPUs raise segmentation faults; the C910 rounds reported fault addresses up to the next multiple of 16 when the address modulo 16 is greater than 8; the C908 raises segmentation faults for valid non-aligned addresses where the correct behavior is a bus error. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[18] The GhostWrite bug is in the v0.7.1 vector extension: illegally-encoded vector-store instructions generate a segmentation fault on the C906 but no exception on the C910, enabling kernel crashes when physical kernel-range addresses are passed. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[19] The C908 halting instructions are illegally encoded vector instructions close to but outside the vector extension; the C906 halting instructions sit on the edge of the documented vendor extension by exploiting an instruction-encoding edge case. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[20] RISCVuzz automatically finds architectural differences that are in most cases bugs, but determining whether a given difference is a security vulnerability still requires manual analysis, which is in many cases relatively quick due to the small reproducers. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[21] RISC-V is an open ISA developed by the RISC-V foundation, consisting of a core instruction set that all RISC-V CPUs must implement plus optional extensions such as the vector extension. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[22] RISC-V defines User, Supervisor, and Machine privilege levels; access to control/status registers and privileged instructions depends on the current privilege level. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[23] User-space testing of architectural CPU behavior can run in sandboxed environments such as Docker containers or Android apps and acts as a filter for security-critical bugs. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[24] Differential fuzzing compares multiple implementations of the same specification and flags behavioral divergences without requiring a golden model; RISCVuzz applies this to closed-source RISC-V CPUs by executing instruction sequences from user space and comparing architectural state such as register values and changed memory contents. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[25] Discovery challenges include the large instruction-sequence search space, nondeterministic architectural effects that complicate comparison (such as performance-counter values and OS-controlled memory mappings), and the closed-source nature of many commercial CPUs. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[26] Transient-execution vulnerabilities such as Meltdown and Spectre follow the architectural specification and leak data only through microarchitectural traces, which limits them to read primitives. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[27] The Pentium F00F Bug is an example of an architectural CPU vulnerability that allowed unprivileged users to lock systems via an invalid instruction. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing

[28] RISCVuzz discovered numerous additional architectural bugs in the tested CPUs and in emulators within seconds of fuzzing. RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Fuzzing