constrained random generation

Constrained Random Generation

Technique

Constrained random generation (CRG) is a verification technique that specifies and solves constraints to produce test stimuli, yielding better tests than pure random generation. It is widely used in simulation-based hardware and property-based testing workflows where input values must satisfy predicates and valid values are sparsely distributed.

First seen 8/17/2026

Last seen 9/30/2026

Evidence 6 chunks

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WIKI

Definition

Constrained random generation (CRG) is a test generation technique that specifies and solves constraints to produce new tests, creating better tests than pure random generation [Evidence: 670134f7-0bde-4ad8-976a-d761d02305b5; cc935418-ba6d-48b1-bd15-e85c190de33b]. In the property-based testing (PBT) literature, the corresponding problem is formalized as: given a predicate on program values, randomly sample from the set of all values satisfying that predicate, and only those values [Source: arxiv 2511.12253v2].

Role in Verification Workflows

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NEIGHBORHOOD

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graph · constrained random generation · depth=1

RELATIONSHIPS

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LLM-based Processor Verification: A Case Study for Neuromorphic Processor ← mentions 95% 2e

The paper mentions constrained random generation as an existing test generation technique.

LLM-based Test Generation compares with → 82% 2e

The paper positions LLM-based test generation as an alternative to constrained random generation.

CITATIONS

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7 citations — click to expand

[1] Constrained random generation (CRG) specifies and solves constraints to generate new tests, creating better tests than pure random generation. GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation

[2] The constrained random generation problem in PBT is: given a predicate on program values, randomly sample from the set of all values satisfying that predicate, and only those values; satisfying values are often sparsely distributed. The Search for Constrained Random Generators

[3] Verification workflows at system and unit levels rely on golden reference models, external checkers, and constrained random generation to validate correctness. GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation

[4] Coverage-directed test generation (CDG) uses AI techniques to automate test biasing but requires significant domain knowledge encoded into the AI model. The Search for Constrained Random Generators

[5] Compliance testing does NOT attempt to stress all combinations of instruction parameters, all data values, micro-architectural aspects, or exception-generating behavior; these tasks fall under Design Verification using techniques such as CRG. Verifying all the flexibility of RISC-V within SoC DV test plans

[6] Palamedes synthesizes correct generators using deductive synthesis rules grounded in denotational semantics of generators, recasting recursive predicates as catamorphisms matched with anamorphisms; the algorithm is built on standard Lean proof-search tactics. The Search for Constrained Random Generators

[7] An LLM-based verification workflow generated C and assembly tests compiled into ELF binaries used as RTL-level stimuli, reaching 89% and 91% code coverage on a RISC-V core and a neuromorphic processor respectively. LLM-based Processor Verification: A Case Study for Neuromorphic Processor