LLM-based Processor Verification: A Case Study for Neuromorphic Processor
PaperFirst seen 8/17/2026
Last seen 8/17/2026
Evidence 12 chunks
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35 connectionsThe paper mentions RISCV-DV as a testing tool for RISC-V processors.
The paper employs LLM-based test generation as its primary verification technique.
The paper uses GPT-3.5 as the primary LLM for test generation.
The paper evaluates LLM-based verification on a neuromorphic processor.
The paper mentions Chip-Chat as a related tool for hardware logic design using ChatGPT.
The paper mentions ChipGPT as a related tool for hardware logic design using ChatGPT.
The paper evaluates Xuantie-C910 as the RISC-V processor under verification.
The paper mentions constrained random generation as an existing test generation technique.
The paper mentions CDG as an existing simulation-based verification approach.
The paper mentions coverage-directed test selection as an existing approach.
The paper relies on simulation-based verification as the underlying approach.
The paper uses RTL-level simulation as part of its verification workflow.
Lei Wang is listed as a corresponding author of the paper.
The paper uses block coverage as a verification metric.
The paper uses expression coverage as a verification metric.
The paper uses toggle coverage as a verification metric.
The paper uses ISA coverage to measure how many instructions are tested.
The paper uses prompt engineering to guide LLM test generation.
The paper proposes and introduces the LLM-based verification workflow for DSA verification.
The paper uses assembly test generation for the neuromorphic processor verification.
The paper uses C program test generation for RISC-V processor verification.
The paper uses iterative test refinement through multiple rounds of LLM interaction.
The paper mentions RAVEN as a testing tool for ARM processors.
The paper mentions random test generation as an existing approach.
Several authors of the paper are affiliated with National University of Defense Technology.
Some authors of the paper are affiliated with University of Electronic Science and Technology of China.
Some authors of the paper are affiliated with Defense Innovation Institute.
The paper uses code coverage as an index to evaluate verification progress.
The paper employs hardware-aware test generation targeting specific processor function units.
The paper mentions GPT-4 as the latest version of the GPT family.
The paper mentions Codex as an LLM fine-tuned on code repositories.
The paper mentions DAVE as the first LLM work in hardware design.
The paper mentions novelty-driven verification as a related approach.
The paper mentions TrueNorth as an example neuromorphic processor.
Chao Xiao is listed as a primary author of the paper.