Assembly Test Generation

Concept

Assembly test generation, in the context of LLM-assisted processor verification, refers to the production of test programs written directly in assembly language targeting a processor's instruction set architecture (ISA), used as stimuli during simulation-based functional verification. In the cited neuromorphic processor verification work, assembly tests are generated for a custom neuromorphic ISA, while C programs are generated for the RISC-V (RV64I) ISA. The approach leverages a large language model (GPT-3.5) prompted with instruction-level descriptions to produce loop-based assembly test programs that exercise neuromorphic instructions such as weight and spike loading.

First seen 8/17/2026

Last seen 8/17/2026

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Assembly Test Generation

Definition

Assembly test generation is the production of test programs written in a target processor's assembly language, where each test is a sequence of instructions at the ISA level intended to exercise specific architectural features. In simulation-based functional verification, these assembly programs are assembled into executable binary files that serve as stimuli for the design under test (DUT).

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LLM-based Processor Verification: A Case Study for Neuromorphic Processor ← uses 95% 2e

The paper uses assembly test generation for the neuromorphic processor verification.

LLM-based Test Generation ← implements 90% 2e

LLM-based test generation implements assembly test generation for neuromorphic ISA.

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LLM-based Processor Verification: A Case Study for Neuromorphic Processor USES Extracted graph relationship

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CITATIONS

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[1] Assembly tests are written directly for the custom neuromorphic ISA while C programs are written for the RISC-V ISA in the cited LLM-based verification workflow. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[2] The workflow consists of test generation, compilation & simulation, and result collection & processing, where the only human effort is conversing with GPT-3.5. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[3] Before test generation, GPT-3.5 is taught the function and usage of each neuromorphic instruction (e.g., lw.wv loads synaptic weights from memory into the Weight Vector Register). LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[4] Once taught an instruction, GPT-3.5 generated a simple assembly program with cyclic weights and spike loading using the instruction. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[5] The neuromorphic ISA achieved 91.02% block coverage, while six RV64I instructions (csrrc, csrrci, csrrs, csrrsi, csrrw, ebreak) were difficult to cover from compiled C programs. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[6] The experiment generated 36 C programs for RISC-V and 128 assembly programs for the neuromorphic ISA. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[7] Coverage metrics evaluated were ISA coverage, block coverage, expression coverage, and toggle coverage. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)

[8] Generating correct assembly code for the novel neuromorphic ISA often requires iterative refinement and human collaboration. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)