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Assembly Test Generation

Concept WIKI v1 · 8/17/2026

Assembly test generation, in the context of LLM-assisted processor verification, refers to the production of test programs written directly in assembly language targeting a processor's instruction set architecture (ISA), used as stimuli during simulation-based functional verification. In the cited neuromorphic processor verification work, assembly tests are generated for a custom neuromorphic ISA, while C programs are generated for the RISC-V (RV64I) ISA. The approach leverages a large language model (GPT-3.5) prompted with instruction-level descriptions to produce loop-based assembly test programs that exercise neuromorphic instructions such as weight and spike loading.

Assembly Test Generation

Definition

Assembly test generation is the production of test programs written in a target processor's assembly language, where each test is a sequence of instructions at the ISA level intended to exercise specific architectural features. In simulation-based functional verification, these assembly programs are assembled into executable binary files that serve as stimuli for the design under test (DUT).

In the LLM-based processor verification workflow described by the cited work, assembly test generation is used specifically for the custom neuromorphic ISA, while C-based test generation is used for the RISC-V (RV64I) ISA. The choice of language depends on the nature of the instruction set: assembly is preferred when the tests must directly express ISA-level operations that are awkward to express in a compiled higher-level language.

Role in the LLM-Based Verification Workflow

The overall workflow consists of three parts: test generation, compilation & simulation, and result collection & processing. The test generation stage focuses on creating new tests based on processed coverage results to cover additional possible conditions.

For the neuromorphic processor:

  1. The custom neuromorphic ISA is initially unknown to the LLM (GPT-3.5), so the first step is to teach the LLM the function and usage of each neuromorphic instruction.
  2. Once the LLM understands an instruction, it can generate a simple assembly program that uses the instruction, typically in a loop construct.
  3. The generated assembly tests are assembled into executable binary files that are used as stimuli in the simulator.
  4. After simulation, coverage information (ISA, block, expression, and toggle) is collected and processed.
  5. Verification engineers examine uncovered conditions and provide feedback to the LLM to guide the next round of test generation.

Example: Generating an Assembly Loop for lw.wv

A concrete example from the cited work illustrates the process. The instruction lw.wv rd, imm(rs1) is defined as using rs1 as a base address, imm as an offset to generate the memory address, and loading 32-bit memory data into a weight vector register (wvr) indexed indirectly by rd. There are 128 wvr registers, each 32 bits.

When prompted: "Now we have defined a new neuromorphic extension instruction lw.wv ... Please generate a loop that traverses and accesses all wvr", GPT-3.5 produced assembly code with the following structure:

asm li x10, 0 # Counter for accessing WVRs li x11, 0 # Base address for accessing WVRs loop: lw.wv x12, 0(x11) # Load WVR data referenced by x10 into x12 # ... increment counter and base address

The LLM is then prompted to extend this with spike-loading loops, producing assembly that iterates over wvr accesses and spike vector register (svr) loads using instructions such as lw.sv.

Assembly vs. C for Test Generation

The cited work notes a trade-off between the two languages for test generation:

  • Assembly for neuromorphic ISA: Because the tests are written in assembly directly, higher coverage is achievable. The block coverage of the neuromorphic extension reached 91.02%.
  • C for RISC-V ISA: Because C programs are compiled, achieving full instruction coverage is challenging. Six uncovered instructions in RV64I were csrrc, csrrci, csrrs, csrrsi, csrrw, and ebreak—the first five interact with Control and Status Registers, and ebreak is used as a debugging/breakpoint instruction, none of which are easily expressed in standard C.

Practical Challenges

  • Novel ISA knowledge gap: Generating correct assembly code for novel ISAs such as the neuromorphic extension is difficult for the LLM and often requires iterative refinement with human collaboration to ensure alignment with intended functionality.
  • Manual prompting overhead: Although test generation is automated, the human must still author and refine each prompt conversation with the LLM based on coverage feedback.
  • Iterative refinement: Subsequent test rounds use feedback from uncovered conditions to drive new prompt strategies.

Scale Used in the Cited Experiment

  • 36 C programs generated for the RISC-V (RV64I) ISA.
  • 128 assembly programs generated for the neuromorphic ISA.
  • Coverage metrics evaluated: ISA coverage, block coverage, expression coverage, and toggle coverage.

LINKED ENTITIES

2 links
LLM-based Processor Verification: A Case Study for Neuromorphic Processor USES
LLM-based Test Generation IMPLEMENTS

CITATIONS

8 sources
8 citations
[1] Assembly tests are written directly for the custom neuromorphic ISA while C programs are written for the RISC-V ISA in the cited LLM-based verification workflow. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[2] The workflow consists of test generation, compilation & simulation, and result collection & processing, where the only human effort is conversing with GPT-3.5. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[3] Before test generation, GPT-3.5 is taught the function and usage of each neuromorphic instruction (e.g., lw.wv loads synaptic weights from memory into the Weight Vector Register). LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[4] Once taught an instruction, GPT-3.5 generated a simple assembly program with cyclic weights and spike loading using the instruction. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[5] The neuromorphic ISA achieved 91.02% block coverage, while six RV64I instructions (csrrc, csrrci, csrrs, csrrsi, csrrw, ebreak) were difficult to cover from compiled C programs. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[6] The experiment generated 36 C programs for RISC-V and 128 assembly programs for the neuromorphic ISA. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[7] Coverage metrics evaluated were ISA coverage, block coverage, expression coverage, and toggle coverage. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)
[8] Generating correct assembly code for the novel neuromorphic ISA often requires iterative refinement and human collaboration. LLM-based Processor Verification: A Case Study for Neuromorphic Processor (DATE 2024)