ISA-Formal

Tool

First seen 7/3/2026

Last seen 8/18/2026

Evidence 14 chunks

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

36 connections

Hand-Written Properties uses → 100% 3e

ISA-Formal uses hand-written properties especially in early stages and for debugging abstraction functions.

ARM Limited ← uses 100% 2e

ARM Limited developed and uses ISA-Formal as a key part of its formal verification strategy.

Instruction Set Architecture (ISA) evaluates → 100% 2e

ISA-Formal verifies that processors correctly implement the Instruction Set Architecture.

Pipeline Forwarding evaluates → 100% 2e

ISA-Formal detects bugs in pipeline forwarding and stall logic.

out-of-order execution evaluates → 100% 2e

ISA-Formal is applicable to out-of-order processors and is used to verify them.

Dual Issue Pipeline evaluates → 95% 2e

ISA-Formal handles dual issue pipelines with adapted abstraction functions.

ISA-Formal applies adapted techniques to handle and verify register renaming in out-of-order processors.

Microcontroller (3-stage pipeline) evaluates → 95% 2e

ISA-Formal scales from simple 3-stage microcontrollers to complex out-of-order processors.

Simulation-Based Verification ← compares with 100% 2e

ISA-Formal is compared to simulation-based verification, finding bugs that simulation cannot easily detect.

Instruction Sequence (Stimulus) uses → 100% 2e

ISA-Formal explores sequences of instructions as the primary stimulus for finding bugs.

SystemVerilog uses → 95% 2e

ISA-Formal uses SystemVerilog for implementing specifications and abstraction logic.

Burch-Dill Flushing Refinement uses → 85% 2e

ISA-Formal builds upon Burch-Dill flushing refinement from the academic community.

ARM Architecture Reference Manual uses → 100% 2e

ISA-Formal uses a mechanical translation of ARM's Architecture Reference Manuals to Verilog.

RTL (Register Transfer Level) uses → 100% 2e

ISA-Formal focuses on verifying RTL (Verilog) implementations of processors.

Architecture Specification Language (ASL) uses → 100% 2e

ISA-Formal translates ARM's Architecture Specification Language (ASL) into Verilog for verification.

End-to-End Verification of ARM Processors with ISA-Formal ← introduces 100% 2e

The paper introduces and describes the ISA-Formal verification framework developed at ARM.

Formal Verification implements → 100% 2e

ISA-Formal implements formal verification techniques for processor pipeline control.

Bounded Model Checking uses → 100% 2e

ISA-Formal uses bounded model checking to explore different sequences of instructions.

End-to-End Verification implements → 100% 2e

ISA-Formal is characterized as an end-to-end verification framework verifying from decode to retire.

Abstraction Function uses → 100% 2e

ISA-Formal relies on abstraction functions to convert micro-architectural state to architectural state.

Pipeline Follower uses → 100% 2e

ISA-Formal uses a pipeline follower to propagate opcode and state through pipeline stages.

Instruction Class Enumeration uses → 100% 2e

ISA-Formal enumerates all instruction classes to perform separate checks for each class.

Instruction Fusion evaluates → 90% 2e

ISA-Formal detects bugs in instruction fusion logic such as decoder bugs related to fused micro-ops.

ARM Architecture evaluates → 97% 1e

ISA-Formal is used to verify ARM processors.

ISA specification uses → 95% 1e

ISA-Formal uses ISA specifications as the basis for verification.

Interface Properties uses → 95% 1e

ISA-Formal uses interface properties for components like the memory system.

reorder buffer evaluates → 90% 1e

ISA-Formal uses the reorder buffer as a serialization point in out-of-order processors.

Formal Verification of Processors implements → 98% 1e

ISA-Formal is a tool for end-to-end formal verification of ARM processors.

superscalar processor evaluates → 90% 1e

ISA-Formal is applied to superscalar in-order processors as part of its range.

Architecture Explorer uses → 90% 1e

Architecture Explorer is the tool used to generate Verification IP from the ARM Architecture Specifications for use in ISA-Formal.

Completion Refinement uses → 85% 1e

ISA-Formal builds on completion refinement techniques from Srinivasan's work.

Unconstrained Opcode (Free Stimulus) uses → 95% 1e

ISA-Formal leaves opcodes unconstrained to allow the model checker to explore all instruction sequences.

End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016) ← introduces 97% 1e

The paper introduces ISA-Formal for end-to-end verification of ARM processors.

Assumption-Based Bug Workaround uses → 100% 1e

ISA-Formal uses assumptions to work around known bugs and allow verification to continue.

Subset Behaviour Checking uses → 95% 1e

ISA-Formal uses subset behaviour checking for components like FPUs where full specification is too complex.

Abstract Functions (Oracle-based Verification) uses → 95% 1e

ISA-Formal uses abstract oracle-based functions as a verification approach for certain functional units.