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ARM Architecture

Concept

ARM Architecture is treated in the evidence as a hardware platform that supports compartmentalization, isolation between trusted firmware and operating system, and a specific Cortex-A execution model with TrustZone. The new evidence focuses on ARM as the host for TrustZone (a Normal World/Secure World split with EL0–EL3 exception levels), on ARM hardware-assisted in-process access control using Pointer Authentication and Memory Tagging Extension, and on ARM as an evaluation target for post-quantum cryptography.

First seen 7/3/2026
Last seen 7/12/2026
Evidence 9 chunks
Wiki v2

WIKI

Overview

ARM Architecture appears in the supplied evidence as a hardware platform with specific features used in security research. The evidence treats it in three main contexts: as the substrate for TrustZone-style isolation between firmware and the OS, as a target for hardware-assisted in-process access control using Pointer Authentication (PA) and Memory Tagging Extension (MTE), and as an evaluation architecture for post-quantum cryptography benchmarking.

TrustZone and Normal World/Secure World isolation on Cortex-A

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NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

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RELATIONSHIPS

11 connections
Hypervisor Verification ← uses 90% 2e
Several hypervisor verification efforts target the ARM architecture.
TrustZone ← part of 100% 2e
TrustZone is a security technology in ARM architecture.
End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016) ← evaluates 97% 1e
The paper verifies ARM processors using the ISA-Formal approach.
Trustworthy Specifications of ARM v8-A and v8-M System Level Architecture (reid:fmcad:2016) ← evaluates 97% 1e
The paper presents trustworthy specifications of ARM v8-A and v8-M architectures.
Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Specification (reid:oopsla:2017) ← evaluates 97% 1e
The paper formally validates the ARM v8-M architecture specification.
Examiner ARM Emulator Consistency Checker ← uses 97% 1e
Examiner tests ARM devices against CPU emulators.
Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 (pulte:popl:2017) ← evaluates 97% 1e
The paper provides axiomatic and operational models for ARMv8 concurrency.
Arm Architecture Specification Language (ASL) uses → 97% 1e
ASL is the language used to specify the ARM architecture.
ISA-Formal ← evaluates 97% 1e
ISA-Formal is used to verify ARM processors.
Modelling the ARMv8 Architecture Operationally: Concurrency and ISA (flur:popl:2016) ← evaluates 97% 1e
The paper models the ARMv8 architecture operationally, covering concurrency and ISA.
ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS (armstrong:popl19:2019) ← evaluates 97% 1e
The paper covers ARMv8-A architecture semantics.

LINKED ENTITIES

1 links
TrustZone PART_OF Extracted graph relationship

CITATIONS

5 sources
5 citations — click to expand
[1] In ARM architecture, the Normal World (where Linux runs) and the Secure World (where a Trusted OS runs in TrustZone) share the same physical memory as the OS, with isolation achieved by address ranges. fuzzing paper excerpt (TrustZone / Cortex-A memory layout)
[2] On Cortex-A, TrustZone is structured using exception levels EL0 (User / Application), EL2 (Hypervisor), and EL3 (Secure / Trusted Firmware-A), with the Secure World hosting Trusted Firmware-A. fuzzing paper excerpt (TrustZone / Cortex-A memory layout)
[3] Modern ARM architecture lacks an equivalent of x86 Protection Keys for Userspace (PKU), but newer ARM architectures introduced Pointer Authentication (PA) and Memory Tagging Extension (MTE) for memory safety and runtime exploit mitigation. Capacity: Cryptographically-Enforced In-Process Capabilities for Modern ARM Architectures (Extended Version)
[4] Capacity is a capability-based in-process access control design that incorporates ARM hardware features (PA, MTE) and uses unique PA keys to authenticate intra-process domains, transforming file descriptors and memory pointers into cryptographically-authenticated references. Capacity: Cryptographically-Enforced In-Process Capabilities for Modern ARM Architectures (Extended Version)
[5] PQC-LEO is a benchmarking framework for evaluating post-quantum cryptographic algorithms on x86 and ARM architectures, with greater performance reduction observed for higher-security PQC methods on ARM than on x86. PQC-LEO: An Evaluation Framework for Post-Quantum Cryptographic Algorithms