Overview

ARM Architecture appears in the supplied evidence as a hardware platform with specific features used in security research. The evidence treats it in three main contexts: as the substrate for TrustZone-style isolation between firmware and the OS, as a target for hardware-assisted in-process access control using Pointer Authentication (PA) and Memory Tagging Extension (MTE), and as an evaluation architecture for post-quantum cryptography benchmarking.

TrustZone and Normal World/Secure World isolation on Cortex-A

In the TrustZone paper excerpt, ARM Architecture is described as running a Normal World where Linux runs, and a Secure World where a Trusted OS runs in TrustZone. The text specifies that "in this paper, TrustZone refers to TrustZone for Cortex-A." These worlds share the same physical memory as the OS, but memory is isolated by address ranges. The excerpt's Figure 1.2 depicts the TrustZone architecture for Cortex-A as a separation between the Normal World and the Secure World, listing exception levels EL0 (User / Application), EL2 (Hypervisor), and EL3 (Secure, hosting Trusted Firmware-A) on the Secure World side, and EL0 (User / Application) on the Normal World side. [C1]

The same source uses the ARM Cortex-A TrustZone layout as a comparison point to the RISC-V OpenSBI/Linux layout, noting that in both, multiple software components occupy distinct memory address ranges within system memory and interact through well-defined interfaces. The source discusses the implications for fuzzing: because the OS and firmware are developed independently and share the same physical memory, incorrect input validation or inconsistent state handling at the OS–firmware interface can propagate across components, and these state-inconsistency bugs may be hard to detect by fuzzing that targets only one component. [C1]

Hardware-assisted in-process access control (PA and MTE)

The Capacity paper observes that "the modern ARM architecture does not have an equivalent feature" to x86's Protection Keys for Userspace (PKU). It describes how newer ARM architectures introduced Pointer Authentication (PA) and Memory Tagging Extension (MTE), adapting the reference validation model for memory safety and runtime exploit mitigation. [C2]

Capacity then uses these ARM features to build a capability-based in-process access control scheme. According to the source, Capacity "coherently incorporates the new hardware security features on ARM that already exhibit inherent characteristics of capability," supports the life-cycle protection of domain-sensitive objects from import from the file system to memory placement, and "with intra-process domains authenticated with unique PA keys, Capacity transforms file descriptors and memory pointers into cryptographically-authenticated references and completely mediates reference usage with its program instrumentation framework and an efficient system call monitor." The Capacity prototype is evaluated on an NGINX web server and other applications, with reported overheads of "approximately 17% for the single-threaded and 13.54% for the multi-threaded webserver." [C2]

Post-quantum cryptography on ARM

The PQC-LEO paper introduces a benchmarking framework for post-quantum cryptographic algorithms on x86 and ARM architectures. Its proof-of-concept evaluation finds that "there is a greater performance reduction in implementing PQC methods with higher security on ARM architectures than on the x86 architecture," indicating that ARM is treated as one of the two principal evaluation targets in the framework. [C3]

Scope of this article

The supplied evidence focuses on ARM Architecture as a security- and performance-relevant hardware platform: Cortex-A TrustZone for OS/firmware isolation, ARM hardware features (PA, MTE) for in-process compartmentalization, and ARM as a benchmarking target for post-quantum cryptography. TrustZone is identified by the related-entity data as a sub-concept that is part of ARM Architecture. The prior version of this article (which focused on formal ISA specification, ASL/Sail semantics, ARMv8 concurrency modeling, and verification) is superseded because the new evidence does not cover those topics and none of the prior version's source chunks are present in the current evidence set.