Paper
Paper
388 entities#
1 Verifying Instruction Set Simulators using Coverage-guided Fuzzing
29 2 Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
28 3 Cascade: CPU fuzzing via intricate program generation
28 4 Processor Verification using Symbolic Execution: A RISC-V Case-Study
28 5 Closing the RISC-V compliance gap: Looking from the negative testing side
19 6 Randomized Testing of RISC-V CPUs using Direct Instruction Injection
19 7 Code Generation for Custom Architectures using Constraint Programming
19 8 An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
18 9 RISC Whisk
18 10 Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
17 11 UCAM-CL-TR-984
17 12 Generation of various programs in Verilog/SystemVerilog for testing EDA tools
16 13 Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
16 14 Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking
16 15 Design and Application of a Co-Simulation Framework for Chisel
15 16 Efficient State Space Exploration: Interleaving Stateless and State-based Model Checking
15 17 μCFI: Formal Verification of Microarchitectural Control-flow Integrity
15 18 Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
15 19 RVDFI
15 20 Mutation-based Compliance Testing for RISC-V
15 21 DiffTest-H
15 22 Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
14 23 Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging
14 24 DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification
14 25 Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
14 26 Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms
14 27 Coverage-driven Functional Test Generation for Processor Validation using Formal Methods
14 28 Hardware accelerated constrained random test generation
14 29 A Framework for Guided Test Case Generation in Constraint Logic Programming
13 30 Fine-Grained Code Analysis for Processor Fuzzing
13 31 Generating Test Programs to Cover Pipeline Interactions
13 32 GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
13 33 A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
13 34 Test Program Generation for a Microprocessor: A Case-Study
13 35 Generating an Efficient Instruction Set Simulator from a Complete Property Suite
13 36 Test-Driven Generation of CSPs Using LLMs
12 37 Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
12 38 Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs
12 39 Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
12 40 UVM Based Design Verification of a RISC-V CPU Core
12 41 An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
12 42 RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation
12 43 Generating Instruction Streams Using Abstract CSP
12 44 MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
12 45 LLM-based Processor Verification: A Case Study for Neuromorphic Processor
12 46 Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
12 47 Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
12 48 Code-based Test Generation for Validation of Functional Processor Descriptions
11 49 Search+LLM-based Testing for ARM Simulators
11 50 Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
11 51 Contradiction Analysis for Constraint-based Random Simulation
11 52 Advanced Virtual Prototyping for Cyber-Physical Systems Using RISC-V
11 53 Specification-based test program generation for MIPS64 memory management units
11 54 Testing CPU Emulators
11 55 An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
11 56 Performance of a SystemVerilog Sudoku Solver with VCS
10 57 AI based SystemVerilog TB generation
10 58 Functional Verification of a RISC-V Vector Accelerator
10 59 A Methodology for Validation of Microprocessors using Equivalence Checking
10 60 FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
10 61 Towards a framework for constraint-based test case generation
10 62 UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach
10 63 Single instruction isolation for RISC-V vector test failures
10 64 Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
10 65 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
9 66 Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks
9 67 Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators
9 68 rtlv: push-button verification of software on hardware
9 69 UVM environment for RISC-V processors
9 70 Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures
9 71 UniGen Paper (DAC 2014)
9 72 Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method
9 73 On Parallel Scalable Uniform SAT Witness Generation
9 74 Reusable Verification Environment for a RISC-V Vector Accelerator
9 75 Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review
9 76 Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments
8 77 From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
8 78 Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
8 79 Input and Output Generation for the Verification of ALU: a Use Case
8 80 Hardware Support to Improve Fuzzing Performance and Precision
8 81 Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
8 82 LLM4DV
8 83 Code Generation and Analysis for the Functional Verification of Microprocessors
8 84 Advanced Automation in Formal Verification of Processors
8 85 Automation of Processor Verification Using Recurrent Neural Networks
7 86 μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
7 87 Towards Verified Faithful Simulation
7 88 ProcessorFuzz paper
7 89 TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing
7 90 End-to-End Verification of ARM Processors with ISA-Formal
7 91 HARTBREAKER paper
7 92 A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking
7 93 Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
7 94 EPEX: Processor Verification by Equivalent Program Execution
6 95 Bryant-O'Hallaron Computer Systems Textbook
6 96 GenHuzz: An Efficient Generative Hardware Fuzzer
6 97 Structured Random Differential Testing of Instruction Decoders
6 98 ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard
6 99 Understanding UVM Coverage for RISC-V Processor Designs
6 100 An Advanced Constrained Random Verification Environment for SystemC
6 100 of 388 shown
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