Paper
Paper
376 entities#
1 Verifying Instruction Set Simulators using Coverage-guided Fuzzing
29 2 Processor Verification using Symbolic Execution: A RISC-V Case-Study
27 3 Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
27 4 Cascade: CPU fuzzing via intricate program generation
20 5 Closing the RISC-V compliance gap: Looking from the negative testing side
19 6 Randomized Testing of RISC-V CPUs using Direct Instruction Injection
19 7 Code Generation for Custom Architectures using Constraint Programming
19 8 RISC Whisk
18 9 An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
18 10 UCAM-CL-TR-984
17 11 Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
17 12 Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
16 13 Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking
16 14 Generation of various programs in Verilog/SystemVerilog for testing EDA tools
16 15 Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
15 16 DiffTest-H
15 17 Design and Application of a Co-Simulation Framework for Chisel
15 18 Efficient State Space Exploration: Interleaving Stateless and State-based Model Checking
15 19 RVDFI
15 20 μCFI: Formal Verification of Microarchitectural Control-flow Integrity
15 21 Coverage-driven Functional Test Generation for Processor Validation using Formal Methods
14 22 Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms
14 23 Hardware accelerated constrained random test generation
14 24 Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
14 25 Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
14 26 A Framework for Guided Test Case Generation in Constraint Logic Programming
13 27 Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging
13 28 GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
13 29 Test Program Generation for a Microprocessor: A Case-Study
13 30 Generating Test Programs to Cover Pipeline Interactions
13 31 Generating an Efficient Instruction Set Simulator from a Complete Property Suite
13 32 Fine-Grained Code Analysis for Processor Fuzzing
13 33 A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
13 34 Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
12 35 Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
12 36 Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs
12 37 RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation
12 38 Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
12 39 MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
12 40 Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
12 41 LLM-based Processor Verification: A Case Study for Neuromorphic Processor
12 42 UVM Based Design Verification of a RISC-V CPU Core
12 43 An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
12 44 Test-Driven Generation of CSPs Using LLMs
12 45 Generating Instruction Streams Using Abstract CSP
12 46 Code-based Test Generation for Validation of Functional Processor Descriptions
11 47 Advanced Virtual Prototyping for Cyber-Physical Systems Using RISC-V
11 48 Contradiction Analysis for Constraint-based Random Simulation
11 49 Search+LLM-based Testing for ARM Simulators
11 50 An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
11 51 Specification-based test program generation for MIPS64 memory management units
11 52 Testing CPU Emulators
11 53 Mutation-based Compliance Testing for RISC-V
11 54 Performance of a SystemVerilog Sudoku Solver with VCS
10 55 Functional Verification of a RISC-V Vector Accelerator
10 56 Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
10 57 Single instruction isolation for RISC-V vector test failures
10 58 AI based SystemVerilog TB generation
10 59 A Methodology for Validation of Microprocessors using Equivalence Checking
10 60 FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
10 61 UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach
10 62 Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
10 63 Towards a framework for constraint-based test case generation
10 64 Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks
9 65 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
9 66 Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators
9 67 Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures
9 68 rtlv: push-button verification of software on hardware
9 69 DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification
9 70 On Parallel Scalable Uniform SAT Witness Generation
9 71 Reusable Verification Environment for a RISC-V Vector Accelerator
9 72 Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method
9 73 UVM environment for RISC-V processors
9 74 Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review
9 75 UniGen Paper (DAC 2014)
9 76 Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments
8 77 From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
8 78 Input and Output Generation for the Verification of ALU: a Use Case
8 79 LLM4DV
8 80 Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
8 81 Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
8 82 Hardware Support to Improve Fuzzing Performance and Precision
8 83 Code Generation and Analysis for the Functional Verification of Microprocessors
8 84 Advanced Automation in Formal Verification of Processors
8 85 Towards Verified Faithful Simulation
7 86 ProcessorFuzz paper
7 87 HARTBREAKER paper
7 88 TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing
7 89 A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking
7 90 μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
7 91 Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
7 92 Automation of Processor Verification Using Recurrent Neural Networks
7 93 End-to-End Verification of ARM Processors with ISA-Formal
7 94 Bryant-O'Hallaron Computer Systems Textbook
6 95 An Advanced Constrained Random Verification Environment for SystemC
6 96 Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing
6 97 Understanding UVM Coverage for RISC-V Processor Designs
6 98 COMS30026 Design Verification: Stimuli Generation
6 99 Guiding Greybox Fuzzing with Mutation Testing
6 100 Structured Random Differential Testing of Instruction Decoders
6 100 of 376 shown
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