Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments
PaperFirst seen 8/13/2026
Last seen 8/13/2026
Evidence 8 chunks
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
30 connectionsThe verification environment includes a scoreboard to assess verification completeness.
The verification environment implements a coverage model to assess verification completeness.
The paper uses the OR1200 Wrapper as part of the verification environment.
The paper uses the OR1200 TB main test bench as part of the verification environment.
The paper applies functional verification methodology.
The paper proposes using the ISS as a golden model for CPU verification.
The paper verifies the OR1200 core at the RTL abstraction level.
The OVM-based verification environment uses TLM interfaces for component communication.
The paper verifies the OR1200 core as a benchmark.
The paper evaluates the Or1ksim ISS alongside the OR1200 core.
The paper introduces an OVM-based reusable verification environment.
The paper evaluates the OR1200 instruction set coverage.
The verification environment implements constrained random generation of verification scenarios.
The paper employs coverage-driven constraint random verification for the OR1200 core.
The paper mentions the OpenRISC32 C/C++ compiler used for benchmark compilation.
Waqas Ahmed is listed as an author of the paper.
The paper references ModelSim as a simulation tool used in the environment.
Siegfried Brandstätter is listed as an author of the paper.
Mario Huemer is listed as an author of the paper.
The paper implements a verification environment using OVM.
The paper uses the ISS as a golden model for verification.
The paper mentions formal verification as an alternative approach.
The main test bench includes an interface verification component.
The test bench implements a synchronization mechanism to handle the pipelined DUV.
An empty ELF image is provided to the ISS in the verification environment.
The communication between the ISS and the test bench is synchronized by SystemC FIFOs.
The OR1200 Wrapper is implemented using SystemVerilog.
The main test bench includes a system verification component.
The main test bench includes a virtual sequencer component.
The paper mentions directed test generation as a traditional but insufficient verification method.