RISC Whisk
PaperFirst seen 8/19/2026
Last seen 8/19/2026
Evidence 18 chunks
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39 connectionsRISC Whisk uses a random instruction generator to produce valid ISA-compatible instructions for the processor under test.
RISC Whisk uses ISA-compatible instruction generation for the processors under test.
RISC Whisk targets RISC-V processors as primary design under test.
RISC Whisk also targets processors based on the OpenRISC 1000 architecture such as Mor1kx.
RISC Whisk uses a constraint block to avoid false crashes during fuzzing.
RISC Whisk uses the direct programming interface as a bridge between testbench and memory model.
RISC Whisk uses AFL++ as the software fuzzer for hardware binary fuzzing.
RISC Whisk introduces a new hardware fuzzing methodology leveraging software fuzzing tools.
RISC Whisk evaluates Picorv as one of the five 32-bit processors under test.
RISC Whisk discusses design verification as the broader context motivating the research.
RISC Whisk uses software fuzzing techniques applied to hardware verification.
RISC Whisk uses a sparse memory matrix as external memory to hold inputs and state during fuzzing.
RISC Whisk uses a custom mutator to mutate instructions while preserving valid instruction formats.
RISC Whisk uses an initial input seed consisting of instructions from all opcodes to start the fuzzing process.
RISC Whisk uses hardware-to-software translation to create executable binaries from RTL designs.
RISC Whisk uses memory modeling tailored to different processor memory interfaces.
RISC Whisk uses RTL-level coverage monitoring to evaluate the hardware fuzzing results.
RISC Whisk mentions functional verification as one of the standard design verification techniques.
RISC Whisk mentions formal verification as one of the standard design verification techniques.
RISC Whisk mentions coverage-based verification as one of the standard design verification techniques.
RISC Whisk mentions assertion-based verification as one of the standard design verification techniques.
RISC Whisk mentions emulation-based verification as one of the standard design verification techniques.
RISC Whisk evaluates Mor1kx as one of the five 32-bit processors under test.
Matthew Hicks served as Chair/advisor for the RISC Whisk thesis.
Angelos Stavrou served as a committee member for the RISC Whisk thesis.
Wenjie Xiong served as a committee member for the RISC Whisk thesis.
RISC Whisk was submitted to Virginia Polytechnic Institute and State University.
RISC Whisk uses Verilator as the hardware-to-C language converter and functional simulator.
RISC Whisk evaluates Sodor1 as one of the five 32-bit processors under test.
RISC Whisk evaluates Sodor3 as one of the five 32-bit processors under test.
RISC Whisk evaluates Sodor5 as one of the five 32-bit processors under test.
Nandita Singh is the author of the RISC Whisk thesis.
RISC Whisk uses a mutation tree structure to track how test cases evolve through successive mutations.
RISC Whisk discusses the wishbone interface as a memory interface used by some of the processor cores.
RISC Whisk mentions black-box fuzzing as a type of fuzzing technique.
RISC Whisk mentions white-box fuzzing as a type of fuzzing technique.
RISC Whisk mentions feedback-based fuzzing as an input generation method.
RISC Whisk uses the concept of Program Under Test (PUT) in the context of fuzzing hardware binaries.
RISC Whisk mentions FPGA-based verification as one of the standard design verification techniques.