Input and Output Generation for the Verification of ALU: a Use Case

Paper

First seen 7/28/2026

Last seen 7/28/2026

Evidence 8 chunks

NEIGHBORHOOD

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RELATIONSHIPS

26 connections

Functional Verification uses → 95% 2e

The paper performs functional verification experiments on an ALU.

probabilistic constrained grammar introduces → 95% 2e

The paper introduces a probabilistic constrained grammar for universal stimuli generation.

Arithmetic Logic Unit evaluates → 95% 2e

The paper uses an ALU as a test case for evaluating the stimuli generation approach.

USG (Universal Stimuli Generator) evaluates → 95% 2e

The paper evaluates USG against a built-in generator in a functional verification experiment.

Code Coverage evaluates → 90% 2e

The paper measures code coverage as a quality metric for the generated stimuli.

Production Rules uses → 90% 2e

The paper uses production rules as part of the PCG definition.

grammar constraints uses → 90% 2e

The paper uses grammar constraints to control stimuli generation.

addition with carry operation uses → 95% 2e

The paper demonstrates the generation mechanism using addition with carry as a main example.

bitwise operations uses → 90% 2e

The paper covers bitwise operations in the ALU grammar definition.

carry bit propagation uses → 90% 2e

Carry bit propagation is modeled in the grammar to correctly generate addition results.

fault tolerance mentions → 85% 1e

The paper mentions fault tolerance as the broader research goal.

RISC processor mentions → 80% 1e

RISC processors are mentioned as more complex circuits the framework was previously applied to.

application-specific integrated circuit mentions → 75% 1e

ASICs are mentioned as a domain for which specific stimuli generators exist.

digital signal processor mentions → 75% 1e

DSPs are mentioned as a domain for which specific stimuli generators exist.

test vectors mentions → 80% 1e

Test vectors are mentioned as simpler stimuli that can be generated in simulation environments.

Ondrej Cekan authored by → 100% 1e

Ondrej Cekan is listed as an author of the paper.

constrained random simulation mentions → 75% 1e

The paper references constrained random simulation as a related concept in stimulus generation.

Richard Panek authored by → 100% 1e

Richard Panek is listed as an author of the paper.

Zdenek Kotasek authored by → 100% 1e

Zdenek Kotasek is listed as an author of the paper.

Brno University of Technology authored by → 100% 1e

The paper is affiliated with Brno University of Technology.

Random Stimuli Generation uses → 95% 1e

The paper focuses on random stimuli generation for an ALU.

expected output generation uses → 95% 1e

The paper generates expected output as part of the stimulus.

Reference Model uses → 85% 1e

The paper uses a reference model for functional verification comparison.

ModelSim uses → 80% 1e

ModelSim is mentioned as a simulation environment where test vectors can be generated.

MicroGP compares with → 80% 1e

MicroGP is mentioned as a related universal stimuli generator for comparison.

FPGA uses → 80% 1e

The paper mentions FPGA as a target for fault tolerance checking.