constrained random simulation
ConceptConstrained random simulation is a hardware verification approach in which input stimuli are generated randomly while satisfying declaratively specified input constraints, and the resulting stimuli are applied in simulation to validate design properties. The cited source emphasizes that effectiveness depends on both constraint-solver performance and the distribution of generated solutions, especially for mixed Boolean/integer variable domains.
WIKI
Constrained random simulation
Constrained random simulation is a technique used in hardware verification in which input stimuli are generated randomly, subject to declaratively specified input constraints, and then applied in simulation to validate design properties.[1]
The cited source describes constrained random simulation as a main workhorse in hardware verification flows.[1] In this workflow, two factors are highlighted as especially important to overall efficiency:[1]
NEIGHBORHOOD
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