Constrained random simulation
Constrained random simulation is a technique used in hardware verification in which input stimuli are generated randomly, subject to declaratively specified input constraints, and then applied in simulation to validate design properties.[1]
The cited source describes constrained random simulation as a main workhorse in hardware verification flows.[1] In this workflow, two factors are highlighted as especially important to overall efficiency:[1]
- the performance of the constraint solver
- the distribution of the generated solutions
The same source discusses this problem in the context of stimulus generation over mixed Boolean/integer variable domains.[1] It also presents a hybrid solver based on Markov-chain Monte Carlo methods as one proposed approach for achieving good performance and solution distribution.[1]
Key aspects
- Randomized stimulus generation: stimuli are generated randomly rather than enumerated manually.[1]
- Constraint-driven inputs: generated stimuli must obey specified input constraints.[1]
- Simulation-based validation: the generated inputs are used to validate design properties by simulation.[1]
- Solver and distribution quality matter: efficiency depends not just on finding solutions, but also on how quickly they are found and how they are distributed.[1]
Scope in the evidence
The available evidence characterizes constrained random simulation primarily through its role in hardware verification and stimulus generation, and through the importance of constraint solving and solution distribution.[1]