RISC processor

Concept

A RISC processor is evidenced here as a reduced instruction set processor category, exemplified by the Verified Architecture MicroProcessor (VAMP), a pipelined RISC processor used as a realistic model for model-based test-program generation and hardware conformance testing.

First seen 5/25/2026

Last seen 8/6/2026

Evidence 6 chunks

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Overview

A RISC processor is referred to in the supplied evidence as a reduced instruction set processor. The evidence uses the term in the description of the Verified Architecture MicroProcessor (VAMP), stating that VAMP is a "pipelined reduced instruction set (RISC) processor" based on out-of-order execution.[RISC-expansion-and-VAMP]

Example: VAMP

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NEIGHBORHOOD

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RELATIONSHIPS

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Memory Management Unit (MMU) ← part of 75% 2e

The MMU is used as a benchmark alongside the RISC processor components.

HW/SW Co-Verification using Bounded Model Checking (Große et al., 2006) ← introduces 90% 2e

The RISC processor benchmark used in experiments comes from the HW/SW Co-Verification paper.

Arithmetic Logic Unit (ALU) ← part of 95% 1e

The RISC processor contains an ALU as one of its components.

Control Unit (CU) ← part of 95% 1e

The RISC processor contains a control unit as one of its components.

External Data Memory (RAM) ← part of 95% 1e

The RISC processor includes an external data memory (RAM).

Program Counter (PC) ← part of 95% 1e

The RISC processor contains a program counter as one of its components.

Input and Output Generation for the Verification of ALU: a Use Case ← mentions 80% 1e

RISC processors are mentioned as more complex circuits the framework was previously applied to.

LINKED ENTITIES

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VAMP IS_A Extracted graph relationship

CITATIONS

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6 citations — click to expand

[1] RISC expansion and VAMP characterization Test Program Generation for a Microprocessor: A Case Study

[2] VAMP is presented as a realistic model of a RISC processor, inspired by IBM's G5 architecture, with a formal model developed in Isabelle/HOL Test Program Generation for a Microprocessor: A Case Study

[3] VAMPasm instruction-set composition Test Program Generation for a Microprocessor: A Case Study

[4] Gate-level to assembly-level conformance testing from a formal instruction-set model Test Program Generation for a Microprocessor: A Case Study

[5] Model-based test generation reused the VAMP model and used HOL-TestGen on top of Isabelle/HOL Test Program Generation for a Microprocessor: A Case Study

[6] Verisoft architecture places VAMPasm at assembly level and VAMP at gate level, within a project aiming at formal verification down to silicon Test Program Generation for a Microprocessor: A Case Study