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RISC processor

Concept WIKI v1 · 5/25/2026

A RISC processor is evidenced here as a reduced instruction set processor category, exemplified by the Verified Architecture MicroProcessor (VAMP), a pipelined RISC processor used as a realistic model for model-based test-program generation and hardware conformance testing.

Overview

A RISC processor is referred to in the supplied evidence as a reduced instruction set processor. The evidence uses the term in the description of the Verified Architecture MicroProcessor (VAMP), stating that VAMP is a "pipelined reduced instruction set (RISC) processor" based on out-of-order execution.[RISC-expansion-and-VAMP]

Example: VAMP

The supplied case study presents VAMP as a realistic model of a RISC processor. VAMP is described as inspired by IBM's G5 architecture and as having a formal processor model developed in Isabelle/HOL within the Verisoft project.[VAMP-realistic-model]

At the assembly level, the VAMP instruction set is called VAMPasm. The evidence states that VAMPasm includes 56 instructions, grouped as follows:[VAMPasm-instruction-set]

  • 8 memory data-transfer instructions
  • 2 constant data-transfer instructions
  • 2 register data-transfer instructions
  • 14 arithmetic and logical-operation instructions
  • 16 test-operation instructions
  • 6 shift-operation instructions
  • 6 control-operation instructions
  • 2 interrupt-handling instructions

Verification and testing context

In the cited case study, RISC-processor testing is discussed through VAMP. The authors generate tests from a formal instruction-set model and use those tests to check conformance between the gate-level implementation and the assembly-level model.[Conformance-testing]

The same work reports that the VAMP processor model was reused for model-based generation of test cases, including test sequences generated with HOL-TestGen on top of Isabelle/HOL.[Model-based-test-generation]

Position in the Verisoft architecture

The evidence places VAMP at the hardware layer of the Verisoft architecture, with VAMPasm at the assembly level and VAMP at the gate level. The broader Verisoft effort is described as aiming at pervasive formal verification of computer systems from application level down to silicon hardware design.[Verisoft-layering]

Related concepts and entities

  • VAMP: an evidenced instance of a pipelined reduced instruction set processor and the main RISC-processor example in the supplied material.

LINKED ENTITIES

1 links

CITATIONS

6 sources
6 citations
[1] RISC expansion and VAMP characterization Test Program Generation for a Microprocessor: A Case Study
[2] VAMP is presented as a realistic model of a RISC processor, inspired by IBM's G5 architecture, with a formal model developed in Isabelle/HOL Test Program Generation for a Microprocessor: A Case Study
[3] VAMPasm instruction-set composition Test Program Generation for a Microprocessor: A Case Study
[4] Gate-level to assembly-level conformance testing from a formal instruction-set model Test Program Generation for a Microprocessor: A Case Study
[5] Model-based test generation reused the VAMP model and used HOL-TestGen on top of Isabelle/HOL Test Program Generation for a Microprocessor: A Case Study
[6] Verisoft architecture places VAMPasm at assembly level and VAMP at gate level, within a project aiming at formal verification down to silicon Test Program Generation for a Microprocessor: A Case Study