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RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation

Paper
First seen 7/26/2026
Last seen 7/26/2026
Evidence 12 chunks

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RELATIONSHIPS

27 connections
AMD Zen microprocessor family evaluates → 95% 2e
The paper collects and analyzes errata for AMD microprocessor families since 2008.
RemembERR introduces → 100% 2e
The paper introduces RemembERR as a new large-scale database of microprocessor errata.
RemembERR database introduces → 100% 2e
The paper introduces the RemembERR database as a comprehensive annotated collection of errata.
errata classification scheme introduces → 100% 2e
The paper introduces a new classification scheme for microprocessor errata based on triggers, contexts, and effects.
design testing and validation evaluates → 95% 2e
The paper evaluates gaps in design testing and validation using aggregated errata information.
microprocessor errata uses → 100% 2e
The paper leverages microprocessor errata as primary data source.
four-eyes manual classification uses → 95% 2e
The paper uses four-eyes manual classification to annotate errata entries.
software-assisted classification uses → 90% 2e
The paper uses software-assisted classification to reduce manual classification burden.
design simulation mentions → 95% 2e
The paper discusses design simulation as a testing technique and its limitations.
Formal Verification mentions → 95% 2e
The paper discusses formal verification and its limitations regarding state explosion.
forward-latent errata mentions → 95% 2e
The paper defines and analyzes forward-latent errata.
Intel Core microprocessor evaluates → 95% 2e
The paper collects and analyzes errata for all Intel Core microprocessor generations since 2008.
CVA6 mentions → 90% 1e
The paper mentions the CVA-6 RISC-V core as an example in the context of simulation complexity.
RISC-V mentions → 90% 1e
The paper mentions RISC-V in the context of the CVA-6 core and simulation complexity.
silicon testing mentions → 95% 1e
The paper discusses silicon testing as a design validation technique.
Emulation mentions → 85% 1e
The paper mentions emulation as a testing technique with limitations similar to simulation.
Patrick Jattke authored by → 100% 1e
The paper is authored by Patrick Jattke.
Kaveh Razavi authored by → 100% 1e
The paper is authored by Kaveh Razavi.
ETH Zurich published by → 100% 1e
The paper is published by the Computer Security Group at ETH Zurich.
bug heredity mentions → 95% 1e
The paper studies bug heredity - the sharing of bugs across design generations.
Flavien Solt authored by → 100% 1e
The paper is authored by Flavien Solt.
backward-latent errata mentions → 95% 1e
The paper defines and analyzes backward-latent errata.
Meltdown mentions → 95% 1e
The paper mentions Meltdown as a well-studied bug that exhibits bug heredity.
Foreshadow mentions → 95% 1e
The paper mentions Foreshadow as a well-studied bug that exhibits bug heredity.
RIDL mentions → 95% 1e
The paper mentions RIDL as a well-studied bug that exhibits bug heredity.
ZombieLoad mentions → 95% 1e
The paper mentions ZombieLoad as a well-studied bug that exhibits bug heredity.
regular expression filtering uses → 90% 1e
The paper uses regular expression filtering to reduce the number of manual classification decisions.