Skip to content
STIMSMITH

Backward-Latent Erratum

Concept

A backward-latent erratum is a microprocessor erratum that is reported in a given design strictly before being reported again in an earlier design, i.e., a defect first surfaced publicly on a newer product and then later re-appeared in an errata document for an older product. The concept is introduced in the RemembERR paper (USENIX MICRO 2022) as the temporal counterpart to forward-latent errata and is analyzed alongside them to study how bugs propagate across CPU generations.

First seen 7/26/2026
Last seen 7/26/2026
Evidence 1 chunks
Wiki v1

WIKI

Backward-Latent Erratum

Definition

A backward-latent erratum is an erratum that was reported in a design strictly before being reported in an earlier design. Formally, it is the temporal dual of a forward-latent erratum:

  • Forward-latent erratum — reported in one design and later reported in a later design.
  • Backward-latent erratum — reported in a design and later reported in an earlier design.
READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections
The paper defines and analyzes backward-latent errata.
bug heredity part of → 85% 1e
Backward-latent errata are a subcategory studied as part of bug heredity analysis.

CITATIONS

4 sources
4 citations — click to collapse
[1] A backward-latent erratum is one that was reported in a design strictly before being reported in an earlier design, and is the dual of a forward-latent erratum. Leveraging Microprocessor Errata for Design Testing and Validation
[2] RemembERR presents forward-latent and backward-latent errata figures for Intel Core CPUs; AMD errata documents lack sufficient chronological information for the same analysis. Leveraging Microprocessor Errata for Design Testing and Validation
[3] There is a salient portion of backward-latent errata around the year 2015, which the authors interpret as possibly reflecting a period of reduced errata-disclosure resources at Intel. Leveraging Microprocessor Errata for Design Testing and Validation
[4] In the merged errata dataset, 28.9% (AMD) and 35.9% (Intel) of errata fall into mitigation categories (BIOS/Firmware, Software, Peripherals) rather than 'No fix' or 'Absent'. Leveraging Microprocessor Errata for Design Testing and Validation